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April 1993 




April 1933 Volume 44 • Number 2 


A New Family of Microwave Signal Generators for the 1990s, by Wfliiam W- Heinz, k 

Ronald E. Pratt, and Peter H. Fisher 

BroaEfband FumfameiitaV frequency Syntliesis from 2 to 20 GHz, by Brian P. Short, 
Thomas L Grfsell, and Edward G. Cristal 

A New High-Perfonnance 0.0T-to-2CI-GHz Synthesized Signal Generator Microwave Chain, 

hy William D. Baumgartner, John S. Brenneman, JohnL Imperato, Douglas A Larson, 
Picardo de Mello Per&grino, and GragoryA. Taylor 

Internal Pulse Generator 

Concurrent Signal Qenerator Engineering and Manufacturing, by Christopher J. Bostak, 
Camata S. Kolseth, and Kevin G. Smith 

A Design for Manufacturabrlity. Design for Testability Checkfist 

A New Generation of Microwave Sweepers, by Alan P. Bloom, Jason A, Chodora, and 
James P. Zellers 

Third-Order Curve-Frt Algorithm 

Z A Digital] V Corrected Fractional-N Synthesizer 


/, Microcircuits for the HP 83750 Series Sweepers, by Eric V V, Heyman, Pick K James, and 
Roger R. Graeber 

l^lJiifil^iwdP Hnlgji • Assoct9te Edilor. Charles L Learh - Publication PrtKtuctian Manager, Susisn E. Wright ■ niustralioo. Fenfe D Pigtuni 
" .flfoul. Cindy Rubii ■ Test tnd Measuramtnt DrgsnJislion Uaispn-, FIiHrrdv T,. Avbv 

Advisnry Bjiafd. William W Brrjwn, fnt^gmS^ Cifcutt flus^Jne^s Otmion. Stfnta Dsra. CBUfQtma m Fr^nlf J. Ca^villo, GfBeiey Storage Bmsm, GnsfBY, CaSofsdo • Hflfr\ 
CriDu Miaow3ve Techmlogy Divismn, ^BfjiafJas^ Cs/rftjmja • Derek T Dancj, System SapiJOf^ Dtvtsion, Maunt^m View. UdSifomi0 • Rajesti Daegi. Ctmrrtsfrist Systmjs, 
Omsim. Cijpsnm. Caiitomta » QQ\iq\5S QennEtlari, Gfseiey Hanknpy Dm$m, Gteeiey, iWradb* Gar^ GnrdDn, HP LBbpraiariss. FaioAlta, Califmnia • Mm Gnidy. 
Waitham Divistm, Waltham. Mas^chuselts^ ManJ Hafline, Systems Tschmfogy Di^/tSm, RdseviiiB. C^Hfumb • Bryan Hncig, Lake Stevem insimmB.'ii Divisiofj. 
Evmsn. Washifjgton • ftogiBf L. Jungeiman, Microwave Jschnoiogy Dmsim. Santa ffosa. Cttiffami^ • Paula K. KaFiaTfifc Inkp! Cifrnponsnls D'msion. CorvsiSis. Qt$gm » 
TJiomas F K^BflmBF, Cofgraiio Spwgs Dmsion. djttofaiio Spmgs.'CQbradQ • ftutry B Lee. fifirm)Tl<:$tt Sysisms G{0ap, CupsrUsw, Cdftfomta* M LlDyd, HP Utorstortss 
Japan. Kawassh Jap^!^ • AJIthI Maute. Wsiiibfwn AmiYti{:ai Division. Wal^ttom. Ssm^ny* WFiEhael P. Maore„ VK\ Sysisms Division. iDvsiai^. CQbrdda • Shelley I. 
MjMre, Sao Diego Printer Division, S^nDiBgrr. C^^fforoi^^Ows L Momll, Warf^idl^ Ca^omBf SuppoH Div/sim yovfUain View. Caiifoinia mV^AW^m M. Mowson, Open 
Syslems Sattw^^e Division, Qie!msf$Fii. AfejsaNr/ryse't?^ * Steven J Nafciso. VX! Systems QimiW. Lnveiand ^to/arft? • Bairy Orsolini, Sotiware Jecffnoiogy D<mjon. 
floffff^rfyfl. CHhfuTfiia ■ Raj Oia. Software TsEhnufogy Oivifiun. Momtsin View. CdHfiffms • Nan Han Phua, Asia Fefiphsfals Qivtsm. Singapore-* Ksfn PowltBn, HP 
Utxif^ioriii^. PaioAlM Cff///bmra • Gunt&T RiehesBll, BnhHogsn ittsmmenls Divisim. Bibiin^n, Gsnnsfjy* Usk Sabatejla. Sofuvsrs EngmBunng Sy^^nis Divtsion, ForJ 
Coiiins, Ctyforadom Wicfaef 0. Saunders, Integrated CitEuii Business Dmsiot\. CotyaHis. Qre§m*^t\\^ Sionton. HP iabaratortss Srfsroi. BftStof. &i^/*3df ■ Bang-Hang 
lay., Singapafs fistwofis Operaiton. Singapore* SEephen R UfKJv. Systems iBeiinoiogy Dmsiw. fort toitins, ColufBdg* RicJiard i. W«6ls, Disk MBmory Division., Soim 
lHatiom Jim Wfcllfls. Netwariand System Mana^em&it Divism. %r Culiinsi. Catoratio • Kaichr l^n^Wa, Jfafe? intiPumEnt Oivi$ion. Kote. jlapa/i • Oannis C Ymk, 
Corva^iis Qivisii^. CarvaUh Oregon * SartarB Zfmnier, (kirpofate Engmesr^ PafoMd Cafi^nin 

©ftewfeit-PatfcaRf CqmpanY 1 9^- PHtiM m U: S A IHe Hewf^ti-I^adiand Journal is primed an recyciefl p^ief, 

A [ 1 ri ] 1 9m } It w k I t-PaL- kard Jouma I 

©Copr. 1949-1998 Hewlett-Packard Co. 

A Prograinmable 3-GHz Puise Gefterator by Hans-Jurgen Wagnsf 

Pulse/Data Channel Extends Programmable Pulse Generator Applications, by Christoph 

Design of a 3-GHz Pulse Generator, by PetBr Sch'mzel Andreas Pfaff, Thomas D/ppon, 
Thomas Fischer, and Allan R. Armstrong 

Cooling of the Frequency Divider IC 

A Multirate Bank of Digital Bandpass Fitters for Acoustic Applications, by James W. Wane 

Continuous Monitoring of Remote J^etworlcs: The RMON MIB, by MaUhewJ. Burdick 

The HP &4700 Embedded Debug Environment: A Hew Paradigm for Embedded System 
Integration and Debugging, by Robert D. Groniund, Richard A Nygaard Jr, and John T. Rasper 

The Value of Usability 

The Debug Environment Connection to HP SoftBench 

(-' A Real-Time Oparatmg System Measurement Tool 

A New Perspective on Emulation Hardware Modularity 

Software Performance Analysis of Real-Time Embedded Systems, by Andrew J. Blasciakf 
David L Neuder, and Arnold S. Berger 


4 In this Issue 

5 Cover 

5 Whafs Afiead 

116 Authors 

The Hev^lett-Pacl^ard Journaf is publtshed bimunthiy by the Heiflflctt- Packard Campany tn recagnizs tethriicsl corrlritjuttonB iriirfB by H&wletl-Paekafd 
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April 1R93 Hewlett-P^kar(J Jfjisma] 3 

)Copr. 1949-1998 Hewlett-Packard Co. 

T-, fUl^ T^^,,« 

State-of-the-art designs for three traditional types of microwave signal 
sources — ^the synthesized signal generator, the sweep oscilfatar or sweeper, 
and the pufse generate remake up the bulk of thts issue. AIJ three are consid- 
ered basic test equipment, the syntiiesized signal generator for receiver testing, 
the sweeper for component testing and general-purpose applications, and the 
pulse generator for digital device testing, 

A signal generator provides a stable, low-noise output signal at a precise fre- 
quency and power level and offers flexible modulation capabilities. The article 
on page 6 introduces the new HP 8370 Series and HP 70340 Series synthesized 
signal generators, which have state-of-the-art performance in the frequency 
range of 0.01 to 20 gigahertz, Key to their performance is a new architecture that uses two broadband 
fundamental oscillators instead of the oscillator and multipliers of previous designs, totally eliminating 
unwanted subharmonic frequencies. Details of the frequency synthesis section are in the article on 
page 12 The microwave chain, which divides the synthesized signal and provides for amplitude and 
pulse modulation, is described in the article on page 17. New processes developed for msxed-modei, 
multiple- option production of these generators are detailed en page 30. 

The HP 83750 Series sweepers (pages 38 and 46) produce swept-frequency output signals in the frequency 
range of 0.01 to 20 gigahertz. While previous designs locked the output frequency to a precise reference 
only at the beginning and end of each sweep in continuous-sweep mode, this new design ensures out- 
put frequency accuracy throughout fast analog sweeps. Like the signal generators with which they 
share this issue, these new sweepers use two broadband oscillators to generate their basic signal, 
eliminating multipliers and subharmonics. 

The HP B133A pulse generator (pages 52, 56, and 60) offers pulse repetition rates to 3 gigahertz and 
extremely precise placement of the pulse edges to help resolve subtle timing and signal integrity prob- 
lems in fast digital devices. Available configurations include a single pulse channel, two pulse channels, 
or a pulse channel and a programmable channel that generates data patterns or pseudorandom binary 
sequences. The design makes extensive use of hybrid microcircuits and custom integrated circuits. 

Fundamental to the measurement of acoustic noise is the 1/3-octave real-time frequency analyzer. FFT 
[fast Fourier transform) analyzers are also useful for certain measurements. Taking advantage of recent 
increases in the speed of off-the-shelf digital signal processing chips, the HP 3569A real-time frequency 
analyzer provides in a single handheld package a dual-channel FFT analyzer, a real-time 1/3'OCtave 
sound intensity filter analyzer an integrating sound level meter, and a reverberation time processor. The 
all-digital processing results in very high precision. The article on page 73 describes the HP 356SA, 
focusing on the design of its multirate bank of digital bandpass filters. 

The Simple Network Management Protocol, a computer network management standard promulgated by 
the Internet Activities Board, has been widely accepted in today's open systems environment. Network 
monitors complying with this standard must gather network statistics according to one of the many 
Management Information Bases, some vendor-specific, that have been registered on the Internet The HP 
LanProbe [l network monitor implements the Remote Monitoring Management Information Base, which 
was developed by HP, Novell, ProTools, and other vendors and is enjoying growing support. The article 
on page 82 describes this Management Information Base and its implementation in the HP LanProbe IL 

.^pnl 1993 Hewlett-Packard jQumal 

)Copr. 1949-1998 Hewlett-Packard Co. 

Unseen microprocessor-based systems are fundamenlaf to the operation of many products not thought 
of as computers, such as microwave ovens and modem automobiles. Developers of such "embedded* 
systems need an extensive set of hardware and softvuare tools to help them debug, analyze, and integrate 
these systems. The HP 64700 embedded debug environment (page 90) is designed to provide access to 
these tools with a single, easy-to-use, graphical user interface that conforms to the OSF/Motif standard. 
The debug envtronment offers a high-level language debugger, a reaftime emulation control and state 
anelysis interface, a real-time software performance analyzer interface (see page 107 for a discussion of 
the new software performance anaiyzerl, and other tools, including s dynamic real-time operating sys- 
tem analysis tool, The debug environment can be used alone or integrated into an even more extensive 
set of software development tools under the HP SoftBench environment 

R.P Dolan 


The advanced microwave synthesized signal generators, sweep oscillators, and pulse generator 
featured in this issue depend on state-of-the art hybrid microcircuittechnofogy for performance, 
reliability, and economy. On the cover, some of the microclrcults developed for these products pose 
for a group photograph. 

Wliai s .i 

The June issue will feature the HP ORG A system, a robot arm optimized for automating analytical 
laboratory tasks and other applications with similar needs. Also featured will be the HP Ultra VGA video 
adapter, the MPE/iX operating system, and HP's object-oriented database HP QpenODB. Finally, there will 
be six papers from the 1992 HP Software Engineering Productivity Conference — three are on practices 
for improving software quality, one on an error handling technique, one on configuration management 
for software tests, and one on a user interface development tool 

AprK 1903 llewi&tt-Pa<:kanlJoiirruil 

)Copr. 1949-1998 Hewlett-Packard Co. 

A New Family of Microwave Signal 
Generators for the 1990s 

This family of generators includes both stand-alone and modular versions. 
A new architecture and state-of-the-art technologies result in advanced 

by William W. Heinz, Ronald E. Pratt, and Peter H, Fisher 

Microwave signal generators have been m^or products of the 
Hewlelt-Packard Corai>any over a time franie spanning five 
decades. In the 1950s, klystron signal generators sucli as tiie 
HP 638 and the HP 620 were providing calibrated signals cov- 
eilng nt^^or bands wUh convenient single- knob timing and 
basic modulation capability for testing comnninications wnd 
radar lec elvers. The advent of back ward -wave oscillator 
tubes in the 1960s led to microwave swept frequency souices 
that eould be tmied electronically over octave bandwidths 
and provided efficient component test capability. 

During the 1970s, solid-state VIG-t lined (yltriiim iron garnet) 
oscillators and multipliers replaced tlie tubes, and with tJie 
incorpoiTition of frequency synthesis techniques, new dimen- 
sions in frequency stability, accuracy^ and spectral purity 
w^ere reaUzed over %'ery broad bandwidths. Along with im- 
proved modulation, sweep capabihty, and progranmiability, 
these were die contributions of the IIP 8672, 8673, ^md 8340 
fatnilies of microwave stmrces, which set the standards for 
tiie 1980s. Major enhancemenLs in perfontiance and conve- 
nience were added later in the decade with the indoduction 
of the HP 8360 family of synthesized sources. 

Over the years, the needs of custoniers wht:> use microwave 
sources have become more specializecL Manufacturers of 
wideband receivers must have generators with more modu- 
lation capability Lmd wider frequency coverage, together 
with excellent spectral purity and a low broadband noise 
floor. People testing radars need low" phase noise, acciuate 
power output over a wide dynamic range, ^md flexible, accu- 
rate pulse modulation capability, ("ustoniers working in tlie 
communications industr>' need high -index fre<iuency modu- 
lation and low phase noise, residiial FM, and spnnous fre- 
quency emissions. Other cnstonrers desire lighter weigiit 
and more compact packaging. 

New Signal Generators 

The new HP 8370 and 70340 Series signal generators offer 
cost-effective solutions for these requirements as well as for 
other needs that can be anticipated for the 1090s. The HP 
8370 Series includes not only signal generators for receiver 
test appUcations but also sweepers for component test and 
general-purpose applications. Tlus article and the articles on 
pages 12. 1 7, ;ind 30 discuss the design and manufacturing of 
the HP 8;370 Series and HP 70340 Series signal generatoi's. 
The sweeper members of the IIP 8370 family are known as 
the HP 83750 Series, and are described in the articles cm 
pages 38 and 46, 

Six HP 8370 and 70340 signal generators have been intro- 
duced so far (see Table I). Four are in standard-rack- width, 
5,25-inch-liigh packages and two are in Modular Measurement 
System (MMS) format 

Table 1 


VTi pro wave S 

g n a 1 Q e n e rate r Ch a ra cte ri Kti c s 










8373 lA 

1 to 20 

-90 to 

Log AM, 

5.25 in 



FM, Pulse 

high, 35 lb 


0.01 to 20 

-90 to 

Log AM. 

5.25 in 


+ IOdBm 

FM, Pulse 

high, 35 lb 

83711 A 

1 to 20 

-90 to 


5.25 in 


+ 10d3m 

high, 35 lb 


0.01 to 20 

-90 to 

CW Only 

5.25 in 



high, 35 lb 



-90 to 

Log AM, 



+ 10dBm 

FM, Pulse 

MMS, 19 lb 


0.01 to 1 

-90 to 

Log AM, 


GHz ex- 


FM, Pulse 

MMS, 5 lb 


The HP 8370 Series represents the stand-alone members of 
the family. Tlus series includes tw^o signal generators pro- 
vided with modulation capability optimized for receiver test 
applications. The HP 83731 A (Fig, 1 J covers the frequency 
range from 1 to 20 GHk, aiKl the HP 83732A adds RF and IF 
test capabilityj covering tlie full lO-MHz-tO'20-GHz range in a 
single J compact (17-mch-deep) package weighing less than 
35 pounds, approximately half the w^eight of the previous 
generation of sources. Modulation capability includes high- 
performance pulse modulation (rise and fall times <10 ns 
and 80'dB on/off ratio). AM perfonuance has been enhanced 
to provide logarithmic (-10 dB/volt) response do\'VTi to SO 
dB, suitable for antenria scan simulation imd deep power 
sweeps for amplitude compression testing of receivers 
and subsystems. With the new wideband FM capabihty; 
modulation indexes exceeding 300 are possible. 

The HP 83731 A and &3732A feature a built-in pulse source 
that provides pulse rates from 3 Hz to 3 MHz ^uid pulse 
widtlis from 25 ns to 419 nis. Tlie pulse source can be se- 
lected from the front panel or an external controller. In trig- 
gered mode J delays of ±419 ms are available for pulse return 

6 ApriJ 1993 Hewteu-Packaid Joiimat 

)Copr. 1949-1998 Hewlett-Packard Co. 

Fig. 1. The HP S3T3IA s>Tithe- 
sized ^igiiaJ generator is repre- 
sentative of the stand-alone HP 
8370 Series signal generators. 
This l-to-20-GH:! mstniinent has 
modulaiion capability aptinuzed 
for receiver test applications. 

siniulation or other apphcations. In addition, tliere are pulse 
doublet and externally gated burst modes of operation, use- 
ful for receiver shadow-time measurements and siinulatuig 
various real-world signals. 

There ;ire many nieasuremeut situations in which it is de- 
sirable ro have the very acnirate level calibration available 
at the front-panel RF connector of the signal generator 
transferred to a remote point in a system where lengths of 
cable or losses mtrodiicx^d after switch boxes have degraded 
the flatness of the sign^il. The user level correction featiu'e 
aJlows this to be accomphshed by connecting a pow er meter 
at the remote point with an HP-IB (IEEE 488) cable between 
it anti tlie signal generator. Tlie generator cajt c^ontrol the 
power meter and store correction factors in memory (four 
tables can be stored with up to 401 i>oints each), t .alibrated, 
flat powder levels then become available for accurate 
measurements at remote ports. 

The oUier two signal generators of tiie HP 8370 Series are 
the HP 8371 lA and 837 12A, which are CW sources designed 
for testing where an economical source withoiu modulation 
capability is neederL such as in exciter ajid loc;?d oscillator 
apphcations. Sufficient power (-f-lf) dBmJ for mixer drive Is 
provided with tlie same low harmonic levels (—55 dBc) as 
the versions with modulation. 

reduced size and increased flexibility. To meet this need the 
significant contributions of the HP 8370 signal generators 
have been leveraged into tiie Modular Measurement System 
(JVIMS) platform (see Fig. 2 J. Supporting an optional modu- 
lar display and adding an MSIB'^ interface, the IIP 7034 OA 
offers the same performance as its rack-and-stack counter- 
partn the HP 8i3731A, at half the size and two thirds the 
weighL A companion unit, the HP 70*341 A, is a one-slot MMS 
module ibat extentis the HP 70340A*s capability to cover the 
O.Ol-to-SO-GHz frequency range. The state-of-the-art accu- 
racy of tlie HP 8370 Series signal generators is maintained in 
tlie modular versions by using the same overall architecture, 
wMch ailoW'S the modular products to be partitioned so that 
interchangeabiUty of modules is achieved without any need 
for recal i brat ion- 

Tlie HP 70341 A Irequency extension module contains O.Ol-to- 
1-GHz dividers, amphfiers, modulators, and filters. Accurate 
power output is maintained by placing the low^-frequency 
leveling detector inside the IIP 703 1 OA. This allows the fre- 
quency response characteristics of the 0.01-to-l-(.Hlz path to 
be calibrated imd stored in the nonvolatile memory of the 
IIP 703-lOA. Correction factors for the nonlinearit ies of t he 
pulse and sciin tUDdulators Ciin be ctilibraietl separately and 
stored in the iiotivolatiie memory provided in lite HP 70341A 

Modular Versions 

There is a market segment that has requirements for Instni- 
mentation liiat equds llie best in the hidustry along with 

' JVleasurement Systsms Interface Bus. the mternal bus of the open standard Modular Mea- 
sureraem Sysism, 

Fig. 2. The HP 7034(IA signal 
gpnorat.or is th(^ Mot hilar Mea- 
surement System v£*rsion of the 
HP 83731A. The HP TtlMlA 
frequency extension module 
extertds l.he range of the HP 
70340 A down tu 10 UHz. 

)Copr. 1949-1998 Hewlett-Packard Co. 

Aprt 1 1 99tl Hewiett^Packard Jou ri laJ 

Fig. S* An example of a modular measurament system consisting 
of an IIP 70340 A signaJ generator (highUghted) and an HP 7I500A 
microwave transition analraer 

Tills allows complete interc^haiigeahility of modules while 
maintaining the state-of-the-art. speciti cations. 

Measurement Systems 

hi addition to reducing size aiici providing inierchangeability 
of modules, the HP 70340A can work with other HP MMS 
products to create powerful, compact measurement systems. 
An example is illustrated in Fig. 3, which show^s t.fie HP 
70r340A and the IIP 71500A microw^ave transition analyzer 
working together to obtain sophisticated data. Fig. 4 shows 
the HP 70340A being used with the HP 70M1A pattern gen- 
erator aiKl tlie HP 70842A error performance analj-zer to pro- 
duce a compact, modular 3-gigabit bit error rate test system. 

NeT¥ Signal Generator Architecture 

To pro\dde the improvement's required for tirisnew family of 
signal generators J a tiew architecture was implemented and 
technologies were incorporated that had matured only after 

Fig- 4. A compact J modular S-Gbitys bit error rate test system con- 
sistiiig of the HP 70340A signal generator (highlighted), the HP 
70841 A paltem generator, and the HP 70842 A error perfomiance 

the previous generation of sources had been designed. A 
simplified block diagraju is shown in Fig. 5. Two broadbatid 
YlG-tuned oscillators replace tl\e YlG-timcd osciUalor and 
multiphers employed in past designs and totally ehminate 
the generation of subharmonlc frequencies. Broadband gaJ- 
Uum arsenide (Ga^) monolithic nticrowave integrated cir- 
cuits (MMICs) provide the gain, output power, tuid variable 
atlemiat ion needed to develop the required signals. A bank 
of svtiiched low-pass filters is used to attenuate unwanted 
harmonics without degrading the fidehty of the complex 
nuHhilation placed on the cairier frequency. 

Frequency extension below the 2-GHz lower Imiit. of the YTO 
(YIG-tuned oscillator) is accomplished with microwave and 
RF frequency dividers, which cost less and provide higher 
perfo nuance than the previously used heterodyne low- 
frequency coverage. Precision, low -cost RF modulators 
implemented with surface motmt technology complement 
their microwave coimterparts, 

hi addition to the of GaAs MMICs, improvements in per- 
formance . cost, size, and weight have been attained ttu-ough 
the higt^ levels of integration achieved in the microwave 
chain by incoqiorating Duroid substrate technology to real- 
ize directional {ouplers, swildieSt filters, and inierconnects. 
Previous reliance on multiple micro circuit packages con- 
nected together with coaxial cables has been supplanted 
by the use of just two integrated microcircuit subsystem 

Tlie use of surface momit teclmology for the printed circuit 
btiards provides a high degiee of comjjactness anti weight 
reduction compared to previous signal generators. In addi- 
tion, the levels of performance required for the low-band 
(divider) frequency extension could not have been reahzed 
with the through-hole technolog^v of the past. 

Leverage and Reuse 

A Itigh lev^el of leveraging anci conunonahtj' went into the 
design of the new family of signal generator products de- 
scribed here. Tlie benefits of this approach extend to manu- 
facturing as well, since economies of scaie in fabrication, 
assembly, and test provide efficiency and savings. The micro- 
wave chain subassemblies are idenucal in the HP 83 731 A 
and 70340A. A simple replacement of tJie modulators withui 
these microchcuits with 50-olmi transmission luies is the 
only change required to prodtice one of the CW signal gener- 
ators of the HP 8370 Series. Even the power supply in the 
HP 8J370 Series signal generators is common to all versions 
and is a self-contained, hne-diiven, switching unit. Foitr of 
the six major surface mount printed circuit board subassem- 
bhes in the HP 70340A are icientical to tlie Hf^ 8370 Series 
sigiviU generator boards. The low-band divider board in the 
HP 70341 A is identical to the [ovv-band boaid in the IIP S;370 
Series signal generators. The power supply in the MMS ver- 
sion is driven by the standard 40-kHz, 24-volt power bus of 
tlie MMS mainframe. 

The Modular Measurement System standard has tight speci- 
fications for electromagnetic compatibility. Fig. 6 shows the 
initiai results of emissions testing performed on the new 
family of sources. The modular source met specifications 
without imy of the design modifications that were required 
to make the stand-alone products pass the test. 

8 April 1 993 He wi^-Packard ,JctumaJ 

)Copr. 1949-1998 Hewlett-Packard Co. 


20 GHz 


2 to 10 GHz 

1 la ZO Amptltiei 





210 20 


y' >: SampEmg 


0,01 to 1.0 


Pulse tn 

Log AM in 

Fig, 5. Simplilied block (iiagram of the new signal geEirraior family. Two broadljcind oscillators replace the oscUlator and iniilLipIJers of 
provlous a.rt:hitecliires. 

The modular source can be placed m the same niairifraiiie iis 
the signal analyzer tJiat was used to obtain the data pre- 
sentecl in Fig. 6. This concDtion must not degrade the system 
pt^rfomiaiire. A test was devised that plarecl tlie HP 70340 A 
in close proximity to a modular scalar network analyjcer 
system that has a 140-dB dynamic range. Initial tests showed 
some degradation in network a}ialyzer peiforniance. This 

wiis eliminated by comiecting a 50-ohm load on the 0.5-to- 
I'GHz output of the sigtial generator and repairing a cracked 
solder joint on a coaxial cable. Rctesting showed that the 
presencx^ of the HP 7(>*i4()A could not be detected by the 
wlde-dynaiuic-rftnge tracking generator system. Passing tliis 
lesf. successfully is evidence of tiu* EMI performance of the 
MMS platfonn. 


Aneit 10 dB 








VflW 10 kHz 

Stop 230 MHz 
Swp too % 

Hef BO.O dS|iV 




Part 4 




Start 30 MHz 

Res BW 30 kHz 


Stop 230 MKz 
Swp 500 ms 

Fig. 6. Iiijtial radiated emissions t{*st results for st^md-aloJiu (leh} imd niodukir (nglil J prototype signal Mf^JK:?rHtorf;. Tru> modular unit inv.l 

flu- NiK:t;ifl('ation wliile the stand-alone unit rHC|tiirc^il furthi^r engineering. The liniilfj shown are from MtL-BTI.) 4filBi RE (12, 

)Copr. 1949-1998 Hewlett-Packard Co. 

April mr..^ llt'wIt^U-PfK'kanl Journal 

Because of space coasFtraints, the modulator drive circuits 
had to be squeezed onto the power supply ?joard. These cir- 
cuits already existed on boards that are specific to the HP 
8370 signal generators. Sint-e ihey were designed to fit into a 
standard cell, it was possible to leverage them for reuse in 
the IIP 70340A. The microprocessor board is tilso speciTic to 
the HP 70340A, but is essentially an HP 8:370 CPU board 
with the space used for the front-pai^el interface circuits on 
the stand-alone board occupied by the MS IB inlerface. 


Another example of reuse is in the area of the firmware in- 
terfaces that exist between the hardw^are and the end user. 
Many instnmients contain more computer power than was 
available in a smaU mamf rame a decade ago. Tlie finuware 
that controls this power has to be designed just as carefully 
as the microwave circuiti>. Reuse of finuware has played u 
key role in the development of this new family of signal 

A greatly .simplified model of tlie sije^al generator firmware 
is shown in F^g. 7, which indicates the major processes that 
must be controlled by the resident operating system when 
the instniment is in its normal mode of operation. All but 
one of these processes were reused from past efforts, so we 

were able to concentrate on developing the instrument exe- 
cution routuies thaf are a mi\jor ctjntributor to the high per- 
formance of the produc^t family. The display haiidlerj front- 
panel interface, and error handler processes were leveraged 
from the development efforts of several other products. A 
significant contribution was a hardware independent SCPI 
(Standard Commands for Programmable Instmment-s) 
parser supplied by HP's Instrument Controller Laboratory. 

The front-panel processes shju^e a common database that 
contiiius the requirements that aie specific to each product. 
The token executor is a small process that receives and out- 
puts staudiirdized messages in the form of tokens. The oper- 
ating system ensures that the tokens are processed in a se- 
quential manner A nnitiue dalabase for each instniment 
defines the actions of Ihe token executon 

Low Cost of Ownership 

Each signal generator application has specific needs. The 
basic aichitecture of this new fainily of sources addresses a 
variety of these needs with an implementation yielding cost- 
effecrive solutions. Total cost of owTtership is minimized by 
pow^erful internal verification capabilities, which can quickly 
isolate a fault to a given subassembly and retluce the meai\ 
time to repair to about four hours. The calculated mean time 

Stiafed Database between 

Stand 'A lone Products 

and MMS 

l^umbar Building IntarmatiDit, 
Front-PaneJ State InJomatiDn 






Data / y 


display IfifDirnatian, 
Aiuioiatiuii Text 



Number Farmatling, 
Di^ptay State 
Informal ion 







Error Messages 




Limits. Resolutionr 
Instrument State 
laformetton, E»iecute 
Routine Pointer. 
Display Information 

Shared Database 

between Stand -A lone 

Products mi MMS 




y Event 

Ftont" Panel 
Error Queue 

SCPI Error 


(n^trument Hardware 

Fig. 7. Overview of the HP S3TQ 
Series aitti 70340 Sf^ries si^ml 
generator firaiwaie. Six aiajor 
proresses are controlled by the 
rf si dent operating system. 

1 April 1 9^ Hewlett-Packard Jouni^ 

)Copr. 1949-1998 Hewlett-Packard Co. 

before failure is greater tiian 20,000 hours (about 10 years of Barber, as the project manager at the beginning of the proj- 

normal use) and the recommended recalibration cycle has ect. made contributions to Ihe definition and to the design, 

been extended lo two years. Ron Larson, Gar>^ Rosen, and Ed Cirimele did a great job 

making the modular products a reality. Bob Skinner played a 

Acioiowledgments key role helping us apply surface mount technologj^ to new* 

Many of the people who contributed to the products de- high^erformance designs. Bill Wendin, Mark Johnston, and 

scribed here are authors of other articles in this issue. Be- Paul Zander were instrumental in pro\1ding the finnware. 

hind all of us Is a large group of people who contributed to Speeial thanks go to Bob DeVries and Phil Foster, who de- 

making the project a success, Tim Carey and Lamn Chroust veloped the product d^ign concepts that made the entire 

provided key marketing support for the program and Al product family a reality. 

ApiH 1093 Hc*wlett'Pat*karid Jotunal 1 1 

)Copr. 1949-1998 Hewlett-Packard Co. 

Broadband Fundamental Frequency 
Synthesis from 2 to 20 GHz 

A broadband fundamental YIG-tuned oscillator is locked to a stable 
reference and controlled by four phase-locked loops to produce the 
low-phase-noise output signal of the HP 8370 and 70340 signal 

by Brian R. Short, Thomas L. GrJsell, and Edward G. Cristal 

The frequency syiUhesi-s subsysltnii of the IIP 8370 Series 
aJKl HP 70^HO Series synthesized sigiuil generators produces 
a stiible, aecurale microwave carrier signal ut the frequency 
rartge fron^ 2 lo 20 GIIz and dehvers it to the nnicrowave 
subsysterti, wliich is described in the article on page 17. Also, 
it is in the frctineney synthesis subsection that frequency 
nio<l Illation is applied to the canier 

Fig, I is a simplified diagi'ani of die microwave osciUator 
phase-loc*ked loop used in the IIP 8370 and HP 70340 signal 
generator families. Both VCOs in the diagram (the reference 
VCO and tJie LOJ are locked to a common stable frequency 
reference (nol shown in tlve Hgure). The piuise/fretjuency 
detector outputs a volliige iiropon ional lo the differ- 
ence between the reference Vt'O mid IF frequencies^ wliit^h 
iifter filtering and uitegration tmies the mirrowave YIG-lunect 
oscillator (YTO) hi a dhection to drive the phase difference 
error to zero, 

FYequency mofiulation, when used, is simimed into the for- 
waid path of the loop and simuhaneoiLsly modulates the 
microwave oscillator together with the control signal. In 
dcFM mode the phase-locked loop is opened (tiie integrator 
nuUed) aiid only the FM signal modulates the microwave 

Detailed Deseription 

A tnote detailed thawuig of the synthesis subsystem is shown 
in Fig* 2. The microwave oseiUalor is a pair of broadband 

fimdaniental YIG-tuned oscillators eovenng 2 to 10 and 10 to 
20 GHz. Each YTO relies on a high-Q yttrium iron ganiet 
device whose resonant frequency is proporiiond to its inter- 
nal magnetic field. The YTO tuning circuitry consists of two 
windings that control the magnetic field: a main coil, which 
c arries the dc control current and sets the CW frequency, 
and a much sm tiller winding that lias a broad frequency re- 
sponse, which is used for ac control and FM. The YTO sys- 
tem is locked to an internal 10-Mllz frequency standard or to 
die user's external source by the i)h;ise-locketi loop, hYequen- 
des between 1 and 2 GH/, are derived in the mit rowave sub- 
system by dividing die "Z-tfyA-GU/. Ijand. Fre<|ueneies between 
10 MHz and I GHz are obtained by additional dividers located 
on the low-band subsystem printed circuit board. ALC (auto- 
matic level control), AM, and pulse modulation are added m 
the microwave subsystem. 

The frequency synthesis subsystem consists of four phase- 
locked loops: the reference oscillator !oop, tlie iocal oscUIa- 
tor loop (LfJ loop), the offset oscillator loop, and the micro- 
wave YIG oscillator loop (YO loop). The entire subsystem, 
excluding die .saiTipler and the YIG oscillatons, resides on 
three surface rtioimt printed circuit tio^irds. Tlve main coil 
driver and its associated filters, amplifiers, and chgital com- 
munication circuits reside on a 4-by-l 1-inch board. Tlie YO 
loop, offset oscillator loop. FM diiver, and associated digital 
commiuiication cucuitiy reside on one -l-by-15-inch board, 
and the LO and reference oscillators and their associated 


Reference ^^^^"^^^ 
Dei eel ar 









Fig. 1. Basic IF-type phiise -locked 

loop used in the HP 8370 and 
70340 Series signal generators. 

1 2 April I mi Hi-wkH 1 -Put kard Jimm al 

)Copr. 1949-1998 Hewlett-Packard Co. 

YD loop 




2 to 20 GHz 


O.QI to 2D 


MAffi Coil 







1310 20 MHz 



IF Samplef 





3 MHz 




Extern el 


digital coitmiunication circuits reside on a second 
4-by- 15-inch board. 

A quirk tri[> arnnntl Hu* YO lo<jp in Pig. 2 shows its basir 
operalion. A small aniouni of die YTO signal neai^ die output 
of the instniment is sampled by a broadband transniission- 
line directional coupler and routed to tJie sampler; which 
acts as a haiTuonir niixer. Tiie sampler, driven hy the \Xy 
loop, produces a comli otliari iconics which d^rwu-convertii 
tlie microwave signal to the intermediate freqiieuc^y (IF). 
The IF ajid extraneous mixing products are heavily Altered 
by the 5-to- 140-MHz bandpass filter, tJien ampliiiedj harfl 
limited, and t*onverted to digital pulses. 

The digital signal is divided by 2, increasing the effective 
dynamic range of the i>hase/frequency detector, and I be- 
comes one of die two control signals used for phase ( oni- 
parison. The other control signal to the phase/freciuency 
detector is generated in the offset oscillator loop. This loop 
provides the fine frequency resolution for tlie synthesi>i;en 

The phase/frequency detector provides a net positive or neg- 
ative voltage when the IF and (JlTsei (tst illnior hTquencies 
ai-e different. When t he IF iuid f>nset oscillaitir signals have 
the same frequency the detector [jroduces a voltage propor- 
tional to their phase difference. \w both silnalions, I he inte- 
grated error voltage tunes die VKi osciilalor fretiuency in a 

Fig. 3. t^iof k diagram of Ihe fre- 
quent cy .synthesis section 0! the 
HP 8ci7U SeriRs and m340 Series 
syrtthesbied signal generators. 

direction to drive the error to zero. Wlien the error voltage is 
zero, the \1G oscillator is ijhase-loc ked and remaiiis locked 
because of the action of the integrator. 

The error voltage from the integrator is frequency-diplexed 
so that higher-frequency components are routed to the low- 
inductanre FM coif while dc and lower-frequency compo- 
neiits aie transfen'cd tcj ilie main ctjiL The frequency diplexer 
cutoff frequency is about Ti Hz. 

Frequency Modulation 

PYcquencies wilhin I he loop bandwidth of the YO phase- 
locked loop are tracked out l)y the action of tlie loop. Conse- 
quenlly, FM rates must exceed the YO Uxjp bandwidth lo 
modidate the VTO, To achieve the required FM bandwidth 
{ 1 kila to I MHz in the HP 8370 Series) the YO loop l>arid' 
widlb is reduied to nboul 6t)(l Hz from its nominal 3(1 VW'i. 
The liigli end is limited by the chiuact eristics of the KM coil. 
Some gain and frequency equalization are added in the FM 
drive circuitry to Oatten the overall response ami jjrovide a 
nominal fi-MHz/volt sensitivity and (iOt)-ohm impedance at 
r lie front panel. 

Also iji FM lnod(^ the divlflers iti front of tlie iihase/frc'qnenf^y 
tictector are Hwittiied to <livlde by 04. Tliis bin her increases 
the detector's effective tlynaniic range, thereby allowing a 

)Copr. 1949-1998 Hewlett-Packard Co. 

Aiiril \ Sm. i Ir wk'TI pEickard J<nin>at 13 





















100 Ik 

0rF5ET tHz] 


Fig. 3. Modf^l 837;UA|>ha:se noise perfomiance af ^,9Hft (\Hz and 
+ l(]dBin. 

laj'ge FM modulation index. The modulation index fi is de- 
fined as the peak frequency deviatiotv At divided by ihe 
modulation frequency, fn,. The phase/ftequency detector is 
limited to ±2ji radians, stj we have the result: 


< 2jr. 

Rearranging factors gives: 

Because of practjcal limitations in the phase/frequency 
detector p is limited to aronn*1 '^00. 

Phase Noise Perfor manege 

As previously mentioned, the Y(.) loop is able lo track fre~ 
quency variations witliin its b^uid width. Tins applies to noise 
as well. The larj^est noise coninbul<irs are the VFO, the LO, 
and the offset oscillators. The I/) tnme is increased by the 
harmonic factor of the sampler. Tlie total phase noise al the 
outt)^i< of the YO loop is the YTO phase noise reduced by llie 
opendoof J gain, phis tlw other loops' phase noise contiibu- 
tions. The noise contributions ol die LO and offset osci I la- 
tors are more significant within the YO Loop baiul width, anrl 
the YTO phase noise is the most significant outside of the 
Y<!.> loofi l>rindwidt h. The YO loop bandwidtJi is selected to 
be ai I tie trequeticy at which the frequenry-multiplicfi noise 
of the LO s>iit]iesizer and tht^ free-Rm noise of tht^ YTO are 
about equal. Tlie noise contribution of the offset synthesizer 
is generally insignificant. A typical phase noise plot showing 
single-sideband phase noise as a fiuictiori of t offset fretiuency 
at 9;9&£J GHz and +10 tlBni is shown in Fig. ;3. 

Offset Loop 

The offset loop is the phase-locked loop that sets the fre- 
quency resohition of the HP 8370 and 70341) Series signal 
generators. The offset loop output is phase-compaied with 

the sampler IF output f see Fig. 2). Therefore, the output 
frequency of the instnnuent changes by the same amount as 
any ircquency change in the offset loop. The offset loop has 
an output frequency tuning range of 13 MHx to 26 Mliz. 
Depending on the instrument option ordered, the frequency 
resolution can l>e either I Hz or 1 kHz. 

Ttie offset loop output signal drives tJie divide-by-2 or divide- 
by-64 circuit ahead of thc^ YO k jop pbas(^ detecton Because 
the offset loop is phase-compared with the output of the 
sampler, the spurious and phase noise performance of the 
offset loop trmislates directly to the outfnir of the signal gen- 
erator. Slated ancjt her way, the equation relating the output 
fre^jiieMcy of die offset loop to the output frequency of the 
entire instriiuieni has no factors of frequency midtiplication 
or frequency division. Therefore, given a desired set of spu- 
rious and f >hase noise specifications for the signal generator 
output, the corres|>onding specifications are required of the 
offset loop. 

To obtain the frequency resolution required, the offset loop 
uses a fractional division scheme. A proprietary IC chip ap- 
plies a digitaJ <;orrectJon technique using sigma-delta modula- 
tor teclinology aud inteq^olarive anaJog-to-digital conversion 
to shape the frequency spectnim of the fractional error en- 
ergyJ The shaping of tlie spectnun pushes the fractitjnal er- 
ror energy away from the earner, where it can be Oltered by 
manijnilation of the loop response, Tlie result is a fmctional-N 
phase-locked loop that is noteucimiberefl by tlie sophisti- 
cated error correction circuitry ofpa^st liactional-N phase- 
locked loops. The performance is high and the cost is low. 

A basic block diagram of the offset loop is sht>wn in Fig. 4. 
The VCO tunes from 520 MHz to 1040 MHz. This is a desu^- 
able frequency timing range because the other reference 
loop, the LO loop, has a VCO liiat tunes from 300 MHz to :355 
MHz. In iiny syntliesizerj it is desirable not to have the inter- 
nal phase-locked loo]>s tuning over conunon frequency 
ranges. This is to minimize coupling between syuthesizers, 
which could produce spurious responses. The output of the 
VOO is well-isolated from the tlividers to prevent any spuri- 
ous response from the Vt'O i I self. The flividers include the 
output divider (divide Ity 40), and die prescaler ahead of the 
fractional syntfiesizer IC. The out^^nt of the ft^ctional synthe- 
sizer IC is phase-compared v\ith a 200-kllz reference signal. 
This reference is deriv ed by dividing a 3-MHz external signal 
(traceable l>ack to the K)-MHz crystal) by Ofteen. The iUit- 
puts of the phase detector are summed by a differential am- 
plifier. At the output of the different iiil amphfier, a variable- 
gain stage keeps the loop gain relatively constant. The VCO 
timing constant varies over the tuning range, and the fre- 
quency fli vision number from the VCO to the phase detector 
varies by a factor of 2 to L Both of these factors contribute 





# I 


VCD S20 to 
t04D MHz 


Fig, 4. Offset pliase4ocked loop. 

14 April 11^»fJ:Hlpw]ett-PfiokaniJoiimai 

)Copr. 1949-1998 Hewlett-Packard Co. 

r-WV-41 » II • 




Low Gain 




Higli Gam 



to reducing the loop gain at the high end of the output fre- 
quency ninge. Tlie variable-gain stage compensates for these 
s'ariations. Tlie result is that ti\e phase noise response of the 
loop remains relatively constant over The oufjiut frequency 
range. The variable-gaui stage is followed in the loop by the 
loop integmtor. 

As previously mentioned, the spurious performance of the 
offset loop must be as good as the desired spurious perfor- 
mance of the signal generator output. The actual offset loop 
spurious performance is over 25 dB better than required. 
The plmse noise perfoiTtiance retiuired of the offset loop is 
also set by the desired signal generator phase noise specifl- 
cattons. The offsei loop exceeds tl\e desired ptiase noise 
performance at all offsets from the carrier by at least 30 dB. 
The di\4der at the output is the key to having so much mar- 
gin in the s(>urious and phase noise performance. With fre- 
quency division at tiie output, the spinious responses and 
phase noise iu^e improved by 20 times tiie logarithm of the 
division factor with respect to the caiTicr signal. In the off- 
set loop the frequency division factor is 40, and the resulting 
improvement in noise and spurious performance is 32 dB. 

The only other perfonnmice spec ill cation that affected the 
offset loop design w^ls the swi telling speed. It was deter- 
mined that to meet the instnmient switciiing speed specitl- 
cations, the offset loop nutst switch in less tJian 10 ms. To 
obtain this specification, the loop bandwidth was atUusted 
and a discharge patli for the loop integrator capacitor was 

Microwave Sampler 

The HP B370 Series uses a fundainental YIG oscillator to 
general e the output frequency direclly, instead of imjltiijly- 
ing llie output from a Iowt'r-fr<^juency (jsdllator This r'e<|iiires 
that the microwave sampler be able to operate al the ouiiKil 
frcijuency (as high as 20 GHz) to iirovide dowTi-conversjon 
for frequency c(jntr<^jL The sairipler tised is borntwed fioni 
the HP 5350 Series microwave counters. - It is received 
assembled and tested, mxi] usetl as-is. 

There are distortion mechanisms in the sampler that can 
cause spurious signal products at its output. Some of these, 
in tiini, cat; cause unde*^ired mixing ijrrxliicts in the synthesis 
section ;uid appear at the inslniment outinil as spurious 

Fig, 5. LO loop. 

signals. An algorithm was used to search for the best sam- 
pler LO frequency for each microwave frequency to mini- 
mize spurious signals. These frequencies are stored in ROM 
in the HP 8370 Scries and are used to set the l/> and offset 
synthesizers appropriately for each output fre<|uency band. 

LO Loop 

As mentioned above, the LO loop output is one of the inputs 
to the microwave sanipler. The LO loop. sIiovvtj in Fig. 5^ is a 
diwde-by-N phase-locked loop wilh mi output nmge of 'ddO to 
:J55 MHz in 0.5-MHz steps. Phase noise perfomumce of this 
loop is critical, since its aut|)ttl frerjuency is multiplied in tJie 
sampler to within an IF spacing of tlie ^TG oscillator fre- 
quency. The multiplication can be as high as 66 times the LO 
frequency at 20 GHz, which increases the noise contribution 
by approximately 36 dB. N<jise performance depends on caie- 
ful VCC) design^ fractional division, and a low-noise reference* 

'live VOO is a cost-effective bul high-jjerforrnmice printed 
circuit l>oiird varactor-t.uned oscillator that uses a lejigth of 
solid coaxial cable as the inductive element This reduces 
the vibration sensiti\il:y of the oscillator circuit because of 
tiie inherent self-shielding of the co^ix. 

An important feature of this VCO is the presence of two tun* 
ing inputs: a low-sensitivity input and a high-sf*nsifiv1t>' in- 
put. The phase-locked loop uses the higli-scnsiUvliy input to 
tune the VCO over the required frequency range. The Jnw- 
sensitivlty input has almost constaixt sensitivity m MHz/volL 
This input is lite f>ne on which the loop baiuiwidlh depends, 
so the band wit It t^ iilso remains cotLstant, Constant t>and- 
widtli helps maintain optimum noise tjerfomtance. The VCO 
pJtase noise is typically -122 dB/lIz at a lO-kHz offset. 

Fracdonal division is used in the di%ide-by'N circuitry to aid 
low-noise performance, A straight forward way to achieve 
0.5-Mllz steps in frequency would l)e to use a ().5-.MlIz refer- 
ence mitl n div1de4>y-N divider. This, lu>wever> would ( ause 
a large nuilliplication of the reference noise. Instead, a 30- 
Mllz reference is used, and the 0.5-MHz steps are developed 
by using a fractional fiivlde-by-N circuit. Thus, noise is nudti- 
plied up by a unich smaller factor: 0.5/30 or approximately 
3B dB less than using a 0.5-MHz reference. 

April 1 fKKi Up w] pt t- Parkard , h n imi I 1 5 

)Copr. 1949-1998 Hewlett-Packard Co. 


Ffee- Running 

Time Base or 
Oven Cold} 








10 MHz 

The fractional divider is realized using a combination of ECL 
digital circuits aiid TTL PAL (programmable array logic). It 
operates at (>0 MHz. 

The low-noise reference is provided by the reference loop, 
which is discussed below. 

Much design work went into the whole Lnsinnnent, and the 
LO loop in particular, to achieve excellent EMC (electromag- 
netic compatibility) performance. Again, one of the most 
difficiili aspect.s wa.s the large multiplication factor from the 
LO loop to the instnjnient tnitpiU. Special iJitemal shielding 
was developed for the VCO section on the printed circuit 
hoard to eliminate RF susceptibility of the VCO at its oscilla- 
tion frequency, at^ impnrlaiU aspect to niany users of inicro- 
wave signal generat ors whose applications are in noisy RF 
en^ii'onments that are rich in potentially interfering signals. 

There are no adjustm^ents in tiie LO loop. 

Reference Loop 

The reference l4>oi), shrmii in Fig, 6, provides two references: 
3 MHz for the offset loop and 30 MHz for the LO loop. It also 
allows tlie use of an external 10-MHz reference. The internal 
reference is a IQ-MIiz printed circuit board ci^^stal oscillator, 
which is locked tt* either the external reference or tiic HP 
high-stabilily linu^ base option if one is present. Exteniiil 
referetices are automatically selected when present at the 
rear-patiel coiinector, mid t he instnntient inkToprocessor is 
notified f o r front -p an e I indication. 

Tlve printed circuit board crystal oscillator can lock over a 
range greater than ±^i)(\ Uz and maintains a noise level of 
-156 dBc/Hz m l-kH^ olTstH ai the UO-Mllz output to the LO 
loop. There is one atyustnu^nt to set the unlocked frequency 
of tlie oscillator to accouiU for crystal variations. 

The 30-MHz output is developed by frequencj'-tripling the 
10-MHz signal, atid the ^^MIlz output is derived from the 
30-MHz output by a divi de-by-ten digital cii%4den 

Fig. 6. Rf^ferenee loop. 

An on-board detector senses an external reference and on- 
l}f)ard logic disatiles the imenial liigh-sraliility reference 
while switching the reference phase-lot^ked k)op input to tlie 
extenml reference port at the rear-panel connector. 

Digital and Analog I/O 

Digital control iind readback are done serially usitig 16 bits. 
As a self-check, tlie serial bus is capable of reading back the 
dala sent It can also read status infonnatioti frum the LO 
loop, Uiilock indications are handled by an inteiTiipt sys- 
tem to avoid constant polling overhead for tlie instrument 

Analog voltages and frequencies can he meastired %'ia a 
single-line analog tnis that each boaid ran drive using local 
analog multiplexers. Thus, power supphes, tmie voltages, 
reference fret^uencies, and so on can be measured for 
traubleshooting and functional verification. 


We would like to acknowledge the contributions of Sunia 
l[iuig. Bill Cornelius, fhrnd Eaglet on, and Teny Noc to the 
dev^elopment of the synthesizer subsystem. Sunia designed 
the YO loop, Bill designed the YIG low-frequency driver, 
David cliaiacterizefl the \T0 performance, and Terry 
designed the FM circuitry. 


1. B. Miller and R.J. Conley. "A Multiple Modulator Fractional Di- 
vifler.'* IEEE TtiTtiSftrtiatis tm Insfrumfnfafifni and Mf^osufy^meifit, 
Vol. IM-IO, IK). :i Jutif ifnti. pp. hlS-fim. 

A. S.K. Gibson, "f ralliiini Ai'senlde Lowers C'ost ant I Irnjirovt^s Perfor- 
mance of MitTowave Ccjunters," Hefvktt-Pfiekanl Jourmit, Vol ?I7, 
no. 2, Ft^ljniHjy in8(>, pp. 4-10. 

16 .April Idm Bewteii ^P^ukarri Jourr^al 

)Copr. 1949-1998 Hewlett-Packard Co. 

A New High-Performance 
O.Ol-to-20-GHz Synthesized Signal 
Generator Microwave Chain 

Driven by s broadband YIG oscillator, the microwave chain only divides 
the oscillator output instead of multiplying and heterodyning like previous 
designs. The benefits include no subharmonics and higher-performance 
pulse and amplitude modulation. The major functions of the microwave 
chain are integrated on two microcircuits. 

by Willlain D. Baumgartner, John S, Brenneman, John L, Imperato, Douglas A. Larson^ 
Ricardo de Mello Peregrino, and Gregorj^ A, Taylor 

The microwave chtiin of the HP a370 aiid HP 70M0 synthe- 
sized signal generator fainilies receives the outi^ut of the 
frequency synthesis section (2 to 20 GHz) and creates the 
leveled signal generator output signal (0,01 to 20 GHz). 

The evolution of the microwave chahi was driven by the 
needs of receiver test and local oscillator cu.stoniers for 
higher peifom^ance, and the tJesire to reduce size, weight, 
and cost. The key performance goals were +8-dBni output 
power^ ±l-dB level accuracy^ no subiuirmoiiics, low h^innon- 
ics (-55 dHc). Tast ( 10 ns) high-fidelity pulses, and the capa- 
bility for sinuiltaneous pulse and deep (-60 dBe) amplitude 
modulation to sunidate rotating-iuiterma tx^iri'^imillers (Fig. 1), 

F*revions architecttu'es start with a 2-to43.6-GlIz fundamental 
baiui tnulliply to 2Ci5 GHz, and postfilter with a YIG (yttrium 
iion ganiel ) lllier The freijueui'y control, ALC, AM, FM, mid 
pulse mrMiuliiliun aje situated in lite fundamentai band for 
lower cost. The disafJvantages associated with this approach 
are subharmonics, low^ power, slow pulse rise tjnie (25 tis) 
because of the narrow VlCi tiller^ ajid sknv MI response 
when the AM is sunidtaneous with pulse modulation. 

Pig. I, H(>1 riling ;tntenna ^;|lf f tnini is iU\ example of simuitaneou.s 

piilHt' aiui aiiLjjIilJjdi' nu»liUa:iini. 

The HP 8370/704r30 design takes advantage ot new broad- 
band galliun\ arset\ide (GMs) compfineiits to achieve dte 
performance goals. Fig. 2 is a block diagram of tlie nticro- 
wRve chain. Subhai'monif!s are eliminated by tutnng a pair of 
broadband YlG-tuned oscillators (TTOs) over a 2-to-20-GHz 
range. Six low-pass filters reduce harmonics to less than -55 
dBc. The low-pass filters have wide baiidwidths, so they do 
ru)! slow^ or disloii pulses. Deep AM is linear in clB per volt 
cUid llatr^ess witli frequency is cori'ected to achieve -60dBc 
depth. AM and puLse Etodulation can be used si3"ntiltat\eously, 

Bjoadband noise in the output of a synthesized signal gener- 
ator affects the sensiti%i1y of a receiver under test and de- 
grades noise figure meter accuracy when the signal genemior 
is used as a local oscillaior. In I his design, AM Jioise is mitii- 
niized by maintain i tig liigh power througlioul Uie chain and 
not placing an anxplifier at the outptit to boost power at the 
expense of noise. The YVO del eniiines the AM noise at 
about 20 (IB above the therniid noise level 

High integration Level 

To lower cost while increasing performance, the circuits 
after the YTO are integrated on two principal microcnrctnls, 
called the output module (Fig. 3} aj\d the modulation mod- 
ule (Fig, 4). This maximizes perfonriance by eliminating 
transitions, connectors, and cal:jles tlvat add loss and niis- 
I natch. The circuits; are fabricated on PTFE*-based Durtiid 
substrates <ind therefore c:an be relatively large withotil the 
circtilt cracking encountered wid} b(jth thick and thin films 
on hai'd substrates, which hniits chrcitii. sizes to about an 
inch or so. Both microcircuits aie st)]dt're<i intij plated alu- 
minum housings. To make it possible to use Diiroid sub- 
strates with tradifioiitU chip kuitl wire boi\ding, a bondaljle 
gokl process was developed. Fabrication was simplified by 
careful tolerance analysis and the circuits aie designed to 
eliminate RF" atljustji vents, which can be costly. HF testing is 
diniv at the higher integration level. This improves yields 
over testing tlie Ujwer-levei circuit^s because a microciretiil 
c£m meet tiveraO specifit*ations atul be accepted even 

' PTFE stands tot polytetiatluorDethylenB 

Auril 1 9D3 tlewl<*tl-Pas ■ kiird Jci umal 1 7 

)Copr. 1949-1998 Hewlett-Packard Co. 

Oi/tpui Motfulfl 






1 to 20 

2 to ia GHz 



fMDdulatipii Module 

Plihe Lug AM 
ModiUalof ModtOalor 



UV^ Sarr 



1,5 101 


Laq am Pulse 

ModtilitlDt Modulitor 

Fart ui Out{iiit 




0,01 ia 1 GH? 




0.01 to 


to 9Q dB 

Fig, 2, liU>rk diagraiTi of the n^icrowave thain uf tlvf- HP 8370 and 70340 Series isynthesized ^\g\\^\ j^enerarors. Most of the ntl( rcjcirnuKs are 
iiiipj^rated mto two modules: the* outpuT mrxJule and thi^ mt»dulafioji module. 

though one of its components may extiibit high Joss and 
anotht'i' low. 

Full ho r integration is ar hipved by using tlie aniplifiei's for 
nioic than one function. Tl\e fust amplifier in Pig. 2, in 
addition to boosting power and buffering the YTO from AM 
frt'ciutMU'y pulling, acts as the ALC modulator. The second 
aiii[>iinpr i.s pai1 of tlie pulse modulator. 

Biliary Dividerjii 

The use of binary' frequency dividers to generate the 
lO-Mllz-to-2-Gllz btuid depLuts from the heterodyne systems 
used in previouy broadband signal sources. The decision to 
replace the nucrowave mixers, os(^illa1ors, and amplifiers 
used in heterodyne down -converters with high-speed digilal 
integrated rircuitK was driven by receiver test requirements 
for rt^duced noise, harmonics, and spurious signals. Ad- 
vances in frequency dividers, broadband components for 
inodulalion and leveling, and higti-deiisity suiface mount 
circuits for liamionic filtering make it possible to produce 
tiie divider system at a much lower cost tlian heterodyne 
systems of equivalent performance. 

Heterodyning a secHt>u of the microwave btmd to the 10-MIlz- 
to-2-<rHz spectrum involves design compromises. Mixers 
used in the frequency translation inherently generate in- 
band spurious signals. Drive levels to the mixer are reduced 

to minimize these spurs, decreasing the signal-to-noise ratio 
at the mixer output, Amplilication used to bring the signal 
up to required levels raises the broatlbimd noise flo(jr as 
well. Tlie mixing prtjcc^ss duplicates Ihe microwave phase 
noise dnnai terisUts in ihe liF baiul. Frecjuency dKision 
avoids ihese pruhleins. I'litLse noise iin<\ spurious signals are 
reduced 6 dB with each octave of division. For a 70-MHz 
signal this results in a '36-dB improvement over heterod>Ti€ 
systems. The di\ideis handle moderate power levels and 
result in noise-^floor improvements tip t« 20 dB. 

Frequency <livLsion hitrochices some different design con- 
stiaints. Output w^avefomis are square weaves with a very 
rich liarmonic spectrum. Third haniionics are only 9,5 dB 
below^ th(^ fundjimental and even-order harmonics, theoreti- 
ciiily suppressed, require Filteiing. The harmonic specifica- 
tion 01-55 dBc require*! nilering alter the final amplification 
stages. Increased filtering lu remove divider luinnonics was 
added to the low pass-filter structures at minimal increase in 
product cost. 

The modular nature of the cascaded dividers allowed low- 
cost frequency extension of the multifunction microcircuits 
from the 2-GHz low^ end of the YIX) down to 1 GHz. Signal 
conditioning in the l-to-2-GHz range is niost economic atty 

Fig. 3, OLnjtyl moduJe, 

Fig* 4. Moduladon mfjdule. 

1 8 April imH Hewlett-Packard .hM\ m ii\ 

)Copr. 1949-1998 Hewlett-Packard Co. 

done with the distributed components in the niicrocircuits. 
The extra octave allows the base source to supply the bands 
in the l-to-2-GHz raitge. which used to require several gener- 
ators or a complete heterodyne system. Surface mount tecJi- 
nologj' provides repeatable RF performance for luniped- 
element design of the lO-MIiz-to-1-GHz band. 

Level accuracy is achie\^ed by a radoing ALC loop tiiat is 
accurate o\ner level and tempe ratine and is corrected for 
power flatness variadoti over frequency. 

Output Module 

The first of the two tnultifunction niicrocircuits, tite output 
module (Hg. r>). performs four fimcdons. The first function 
is ?o couple a portion of the oscillator output back to the 
frequency sampler and tlie frequency control subsystem. 
Two flirectjonal couplers, each covering a ^IG-oscillalor 
frequency band, were designed for this puiijose. 

The second function of the output module is to provide 
swiu:hing to route the mkrowav e signal from tlie appropri- 
ate YIG oscillator band through the microwave chain. 
Tlurdly, the output module divitles I he \iG osciilalor output 
in the 2-to^-GIlz range l>y twf> or four to generate signals 
from 0,5 to 1,0 GHz and LO to 2.0 GHz. The 0.5-tf>L04}Hz 
band is used to chive the low-i)and ciicuii hoard, which 
generates outputs in the 0.01-to-l.O-GHz range. 

The fourth funcdon of the output module Ls microwave ^gnai 
processing for the automatic level control (ALC) subsystem. 
A broadband directional coupler detei^tor samples the aver- 
age power incident on the syntliesizer load and feeds back 
the sample to the level control loop circuitrj". The 'variahle- 
gain traveMng-wave amphfier acts as the le^ehng loop control 
element, modulating the microwave power to the desired 

A PTFE-based material, RT/Duroid 5880, was chosen as the 
substrate for the *jutput module. This materiiil has a low loss 
tangent (O.OOOf* at 10 GHz), can l^e processed in a printed 
circuit board shop (resulting in low cost), and can be tised ibr 
lai'ge circuits that Itave contplex outhnes fuitlike a large piece 
of alimtina, which will crack wiien subjected to themial 
stresses after being been laser-routed into a compiicated 

Extensive use w^as n^ade of GAf3 tools in the development of 
the components that are integrated into the output ntodule. 
Tliese tools included hneai' circuit simulators, system simu- 
lators, and graphical layout tools. One extremely useful pro- 
gram, written by Jeff Meyer of HP's Systems Soiutiotts 
Division, computes the solution of Laplace s equation m a 
rwo-dimensional region. Tlie prograrti uses the method of 
moments to solve for the I^aplacian potentiiU. Properties of 
tmconventional transiriission line structures can be analyzed 






J, ^ 



2.0 to 20.0 







lO.fltD 2)0.0 


o.(»no 20.00 

mz In 






Frequencv ^^^^ 


5Vdc Freifuency 

^ — ^^• 



J to to 

±1 Vdc 

V V 

1.0 to 20.0 

GHz Out 



0.01 TO 20.00 

GHz Our 

Reference In 


ifefarence Diode 


Leveling Amplifier 

Levelmg Coupler Deteclur 

Aprtl IM J Jf -wlt^l I Pnr kjirrl .h lum^l 19 

)Copr. 1949-1998 Hewlett-Packard Co. 

Matched to e SOil Transmission Lino 

Matched to a 5011 Transmission Line 

Ground Plane 

Reli&ved 10 Increase 

Impedan^o — ^ 


~ 14&[^ Shunt Tiansfnissian Line 

Flaled -Through 

Fig, G, Printed ground return with shunt stub in a diode a witch 

with the help of this pro^ani, and as a result, it was possible 
to design circuits not realizable with ordinary microstrip 
Irimsmission line. 

Switching in the output module is done with p-i-n beaiivlead 
diodes. Two switches cover the l-to-20-Gllz frequency 
range. One is a double-pole, double-throw switch and the 
other is a single-pole, double- throw switch. It was a design 
goal to use as many printed components as possible to 
lower the assembly cost aivd ensure repeat able performance 
fn*m unU to unit, The printed ground return shown in Fig. il 
provides a dc short while passing init^rowave signals frotn 2 
to 20 GHz with a minimiim ol 20 dB return loss. Tire method 
of moments field solver program was used to design the 
145-ohm characteristic impedance shunt stub in this circuit. 
Since the maximum impedance achievable with a microstrip 
transmission line on a 0.0 tO-incti-l hick liT/Duroid 5880 sub- 
strate is 110 ohms, it was necessary to modify the structure 
by etching tlie gap in die ground plane as sh(j\Mi in Pig. 7. 
The field solver was used to calculate tlie gap widtl^ requhed 
to achieve 145 oluns for a fixed top conductor width of 0.006 
inch- By making Il^h, the transmission line impedance was 


Top Center 
— J O.flOBIn [*— /^Conductor 








Aluminum Mic roc if cult Housing 












Fij^. 7* Cross section of 145-ohm shunt stub- 

Frequency I GHz} 
Fig. 8. Leveling touplerdetecEur trpqiu-nny rosponse* 

made insensitive to manulartnriiig varialions in (he housing 
dimei^sions hikI in the circuit attach process. 

The leveling coupler is an asymmetric, continuously tapered, 
parallel-lhie croupier. The nominal coupling is 2(U1B from 2 
to 20 GHz. An RT/Diucjid 5880 (jveriay. clamped in place 
with a silicone sponge-nil >!)er patl, is used to equalise the 
even-niotle and odd-nu>de velocities. The nietliod of mo- 
iTienis field solver wa:^ tised to design tills structure by gen- 
erating a taljle of odd-mode impedance values versus cou- 
pling gap. This table was tised to s^mthesize a design using 
ideal coupled tjansmission lijies. The directivity of the cou- 
pler is topically better than 16 dB to 20 GHz. Good directiv- 
itT^^ in the leveling coupler results in a good source match 
and output level accuracy for the signal generator. Tlie over- 
lay and sponge clamp are tluck enougli so that (nirrents are 
r^ol iiKkiced in the package M above the cou|)ler. 'fhis al- 
lows a smooth transition to conventionaJ microstrip. A 
broadband microstrip detector using pianai^ tioped barrier 
beam-lead diodes is there foie easily integrated witli the cou- 
pler int{> a single housing. Integrating the leveling t*oupler 
delect or with other circuits into (jne mochtle yiekls subij^ljui- 
I ial cost savings relative to previous signal generator block 
diagrams in which the coujjier was a connectorized compo- 
nent i>urcbasetl from an outside vendor mid the detector 
was separately housed in an expensive package. The inte- 
gi-ated tlesign also allows tlie addition of a reference diode 
for temperatine compensation. Figs. 8 and 9 show typical 
performance for the coupler detector. 

'Two additional microstrip couplers in the outjjut modijle 
cover the 2-to-lO-GiIz ^md 10-t(j-20-Gllz frequency baiifls. 
These couplers are used to feed back the signals from the 
frequency syti thesis section to a frequency sampler The 
constmction of the 2-to40-GHz coupler is similar to that of 
the levelmg coupler. Its coupling ratio is 20 dB at 2 GHz mvi 
rolls off at 6 dB per octave to 10 (iHz. The coupler was de- 
signed this way to reduce the level of hannonics incident on 
the frequency sampler. The lO-to-20-Gllz coupler is entirely 
planar, making it very inexpensive to manufacuire. It is a 
three-section, synunetric coutiler with a nonunal r^S-dB cou- 
pling ratio. The even and odd modes are equalized by a 
printed capacitor at each end of tlie center section. 

20 April imz tIewleit-Packard JounutI 

)Copr. 1949-1998 Hewlett-Packard Co. 








— O.B I 

- -U ^ 

-1.< B 





Frequency (GHz) 
Fig, 9, Lr^veling coupler/detjecior insertion and retttm loss (match). 

The broadband traveling-wave amplifier (described later) is 
housed in a hernietically sealed, ceramic package. This en- 
sures reliable i>erfonnance of this GaAs integrated circuit 
over varied ejivTioimiental conditions such as high humidity- 
and temperature. Careful engineering ensures that the ce- 
ramic package does not degrade Uie nncrowa\'e perfonnance 
of the traveling-wave amplifier chip to 20 GHz. 

T»' o static frequency dividers generate the l-to-2-GHz band, 
which Is s\^1tched back into the 140-20-0112 path, and the 
0-5-to-l-GHz ouq>ut drive for the 0.01-lo-l-GHz divider band. 

Modulation Module 

The functions of the second microcircuit the modulation 
module, include pulse modulalion. amplitude modulation, 
and harmonic filtering, all from 1 to 20 GH2. This module 
also contains a low-distortion combining switch for the 
0.01-to-l-GHz band. The modulation is implemented with a 
O.OlO-inch thin-film alumina circuit on a 0.015-inch molybde- 
num carrier for thermal expansion matching and a hemtetic 
thick-film alumina-packaged traveling-wave amplifier The 
harmonic filiering and broadband combining switch are 
implemented on a O.OlO-inch Duroid substrate. Fig. 10 is a 
diagram of the modulation module, 

AM for the instnuneni is provided by a modulator containing 
Sve shimr p-i-n diodes J Originally designed for pulse modu- 
lation, in this case tl^e moduiaior is used to pro\ide 60 dB of 
logarithmic AM. The transfer function of the AM modulator 
is corrected as a function of modulation deptii and frequency 
wiOi gain and offset DAC (digital-to-anaiog converter) atljust- 
ments. Fig. 1 1 shows the deviation from linearity as a func- 
tior\ of depth tmd fiequency. The driving function departs 

0.01 to 1 
GHz In 

MndulBtioii MicFacircuU 

110 20 
GHz In 




f I 

Pulse Antplrfief 





CF124 CR2S 

CR22 CR21 

CR26 Cfl2S 










Pulse and AM 
Drive; Board 




AM In 



CR28 CR2? 






CR31 CR32 CR33 

CR19 CR1& 





CR4 C3 


CR10 0.01 10 20 




Fig. 10. Block diagram oflhe nioduMitJU niddule, 






April ISSO Hewlett-Packard JouniaJ 2 1 

)Copr. 1949-1998 Hewlett-Packard Co. 



P&ik Pawef Uvel = dBm 

Log AM Error HCHz 

Log AW Error 10 GHz 


Up AM Error 4-20 GHz 








n 5 10 15 20 25 30 35 4fl 45 50 55 6fl 
DesiiGit Log AM Depth (Anenuaiionl (dB} 

Fig, 1 1 , TVpi^il log AM error (deviitlion from difsiri^d fJepth) at 25^C 

for f^irrifr frequencies betw.'^een 1 1) and 20 GHz. 

from ti-aditional A^I iii that it is logarithmic (-1(1 dBA"). Tiie 
log driving function is ideal for simulating largt* djmamic 
ranges like the deep nulls in an antenna scan pattern. 

Pulse modulation for the iiistmrneni is implemented with 
three GaAs ICsi two attenuators iuid (jne traveling- wav^e 
aniplifien Specific at iotis include lU^>io-9tfK)pulse rise and 
faJl times less than 10 lis, puise on/off j^atio > BO dB, < IW 
pulse o%^ershoot, +l-dB pulse level accuracy (relative to the 
CW level), and < 20-mV peak-to-peak video feedtlirough. 
Fig, 12 shows a typical pulse and a typical pulse on/off ratio 

Attenuators. Tl\e attenuators are series-sh tint -series attenua- 
tors fFig, 13). The series elements me common-gate FETs 
with 50-ohni resistors comiected m parallel from drain to 
source. The shunt clement is composed of four common- 
gate FETs connected in parallel with some traiismission line 
spacing bet w^een them- This spacing contributes to a good 

Tlnie isse c 1 0.0 iis/dtv 
Carrier 1^requeiii^y = 1fl.O GHz 

Riso Time ±4,3 ns 
Fati Time = 2.§5 ns 



115 4 


3 12 

Carrier Frequf nc| (GHzj 

-H H 


Fig. 12. (a) T^^pie^l pulse modulation envelope. (I)) Typical pulse 
Eiodulation on/off ratio at +8 dBm. 

FET An«nuatar 







Fig. 13. FKT aitenuator. 

match. It also results in a low^er on/off ratio at low frequen- 
t ies. where the spacmg is negligible compaj'ed to a w^ave- 
length. The gales of the shuni FETs are thiven by signals 
that are complenientary to those thai drive the gales of the 
series FETs. !n the on state the series FETs are on aud the 
shunt FETs are off, al hawing the signiil to puss. In the off 
state the series FETs ;ire off and the sliimt F^ETs ;ii'e on, thus 
connecting the 50-ohm resistors that are in fjarallel with the 
series FETs to ground through the shunt FETs. This main- 
tamis a good match in the off state, mihke p-i-n diode modu- 
lators. This pjeserv'atiou of match in both states contributes 
to the good puls€ envelope fidehty. 

Amplifier. The travehng-wave amplifier is a seven-stage cas- 
code design (Fig. 14). The gates of the comiuon-gate FETs of 
the case ode are used to control the aiuplifier gain. In tlie on 
state, this control is high and the amplifier pro\ides about 6 
dB of gain. In the off stale, this control is low, pincliing off 
the FETs aud turning the amplifier off. In this way the ampli- 
fier coutrihijies to the pulse oii/off ratio. The frequency re- 
sponse is dominated by the gate-to-source capacitance of 
the common-source FETs, so the on/off ratio Ls low^er at 
lugher frequencies. The traveling- w^ave amjilifier thus com- 
plements the attenuators, compensatiug for loss and on/off 
ratio frequency response. Also, the malch of the traveling- 
wave amplifier is maintained in botli tlte on and off states. 

Pulse Performance. Othei- factors that affecl pulse on/off ratio 
are leakages and w^aveguide modes. The main leakage path 
is tlirougli the gate of the first series FET of the first attenu- 
ator, througli the bias circuitry, and into the travehng-wave 
amplifier control. B>passing is reqiured to reduce this leak- 
age to acceptable levels. Waveguide moties are suppressed 
witJi polyiron and narrow charmets in the housing. 

Tlie pulse level accuracw is dommatcd by thermal effects in 
the t rave ling- wa\'e amplifier, hi tlie off condition, tlie ampli- 
fier cools down. When it is turned on, the gain is initially 
Iiigher iuid drops as the dave ling- wave amplifier heats up, 
with a tuue constant on tlie order of 10 Pulse level 
changes are typically about -h0,5 dB from CW leveJs, 

Tlie pulse rise and Pall times are dominated by the traveling- 
wave amplifier switching thne. The bypassing element 

22 April 1993 Hpwlptt-Packjird Journal 

)Copr. 1949-1998 Hewlett-Packard Co. 

Traveling 'Wave Ain{tlifier 






Kg. 14, Traveling- vrave 

requirements impose a lower limit on capacitance at the 
traveling- wave anipliiier control input. Also, there are inter- 
nal capacitors on each of the seven stages' second gates, 
Tlie drive source impedance is nonlinear: the off-state im- 
pedance is low, mid the on-state impedance is 50 ohms, A 
low impedance for the off state provides quick discharging 
of the bypass capacitance, and the matched impedance for 
the on state maintains good pulse envelope fulelity (a low- 
impedajice driver in both states would cause pulse over- 
shoot and ringing). Tlie driver used is simply a low-source- 
impedance circuit with a 50-ohm series output resistor and a 
Schottk>' diode in paiallel with the 50 ohms (Fig. 10). For 
signal generator models witliout AM and pulse modulation 
the carrier circuit is replaced by a through line on a Duroid 

Filters. The < 55-dBc harmonic perfonnance of the instru- 
ment is achieved with a switched low-pass filter assembly. 
Six filters connected betwec^n tA\(> 1P5T (one-pole, G-throw) 
p-i-n diode switches strip the hanuonlcs rmm signals be- 
tween 1 GHz and 20 GHz. The output combining switch also 
includes an extra throw for 0.01 to 1 (tHz» making ii a 1P7T 
switch. Harmonic filtering is not clone for this path. The p-i-n 
diode used for this throw is a l-pts-lifetiuie diode, which 
maintains the harmonic performance down to (MJl GHz, 
Fig. 15 shows typical second'harmonic performance; 
higher-harmonic performajice is typically better. 

Tlie low-pass filters are distributed qiuisi-elliptic low-pass 
filters. They were computer optitnis^ed. emphasising above- 
baiul sjHjrious response. The hjwcr ihrcf^ filters are asym- 
metric^ which gives almost double 1 lie number of distinct 
transmission zeros in the stop band, and they are cascaded 
with five-elemeni, higher-frequency, distributed low-pass 
filters to reduce spurious transmission hands. 








■ I 


-7b - 


V V 


-80 - 


-90 " 

■ \ h— 

-i \ H h 

\^ \ 

-H \ 

2 4 fi a 1C 

Cartier Frgquency (GHz) 

Fig. 15, T^'pioal semnd*hanrionic levels measured al an (uilpui 
power of +6 dBm, 

The next two filters are optimized, synunetiic, distributed 
Chebyshev low-pass filters. Tlte last filter is only four shunt 
stubs on a 50-ohm line. This makes its loss lower, and it is 
easy to cut off the stubs to create a 50'Ohm through Une. Tlie 
fdter cutoff frequencies aie 1.65 GHz, 2.75 GHz, 4.80 GHz^ 
8 GHz. 12.8 GHz, iind 21 GHz. 

Switches. The p-i*n switches are compensated to match the 
off diodes' capacitance. The input splitting switch has four 
series-series arms and two series-shimt -shunt arms, the lat- 
ter for isolation and low Joss at higher frequencies. Tlie out- 
put combining switch has sLx series-shunt arms and a 0.01- 
tO'1-GHziinn fanherdown the line. In the 0.01 -to- 1 -GHz 
arm, tlie long4ife1 inu^ p-i-n dio<le's capacitance serves as the 
middle element of a five-elenient clisl ributed low-pass filter. 

The bias elements are distributed where possible for low 
cost, and all have capacitive feedlhrougbs to connect to a 
standard printed circuit board for bias swhchlng circuitry. 

An example will Illustrate the operation of the switches (see 
Fig, 10), Consider the operation at 2 GHz. Only the LPI^ 
path is biased on and all other paths are biased oil'. Tliis is 
accomplislied by the ai>phcation of + 15V to J 18 imil a nega- 
tive current for M, J5, J 1 2 through J 1 1, and J24. JIO and Jl 1 
are each connected to 330 ohms to ground. The +15V on J 18 
forw'ard biases CH4, CR2t, and CR22, the current being set 
by the voltage and the 330-olim resistors. CKIO is reverse 
biased by this same + 15V. and the path through LPF2 Ls es- 
tablislied. Tiie other pat lis' negative currerUs forward bias 
CR2, CRO, CRl 1 tiuough CR16, CRIB, and CRUi Tins also 
sets up a reverse bias on C^Rl, CR3, ("R5 through CRS, CRl 7, 
C^R20. tmd CE2^ through rR28, Thus the signal can only 
flow through LPP2. An important consideration is that the 
loW'pass filters that are off do not disturb the match. For 
this retison series-only diode switches can't be used. For 
exampk^ if CR9 were not present, LPFTs output reflection 
coefficient, which has magnitude miity and iu'hitrary phase 
because of the line lengths required to connect the cii'cuitj 
could resonate with the capacitance of reverse biased CR3 
to make a short circuit at Ihe output switches common pole. 
The input switch uses series-series diodes to combat the 
same effect, which works only because of the finite Q of the 
reverse blaseti diodes capacitance- 

Low-Band Output Section 

Tht' low-iiand sect i< in (Fig. Hi) provides the tO-MUz-to- 

I -GHz frequency b^md by dividing the r>00~MHz-to-1024-GHz 

signal pn Khued by the divnde-by-four c inn its in the output 

April tyai Hewlf^u-Piftckfin! Journal 23 

)Copr. 1949-1998 Hewlett-Packard Co. 

500 10 1024 Dividers 

t) rtBm from 
Output Module 


TOto 1000 MHz 

ModulBtion lor 
HP B3732A and 70341 A 

Log AM Morfulator 

Output Amplifier and ALC 

Fram ALC 
Cdntrol Board 

lOtD 1000 MHz 
-15 to 4-Z4 dBitt 

Log AM In 

Pulse In Iram 
Pulse Generator 

Switched Low-Pfts^ Filter Assembtv 

500 to 1000 MHz 

64 to 500 MHz 


700 to lOOO MHz 

lOto 22.5 MHz 

Difectional Bridge 

lOto 1000 MHz 
To Modulation 
Module Micf a- 


22.5 to 64 MHz 

and w 

1 B1 10 500 M Hz etector Volts ge 

to ALC Contral Beard 

Low-Pass Fillers 

Fig. 16, Block diagram of the low-haiid output seclion, whirh jjrrmdt^s lO-MMz-to-l GHz freQuency coverage. 

module microcirciiit. The low-band input signal is dividefl, 
amplified, filtered to reduce hamionirs, and deteclefl for 
automatic IcvqI confrol (ALC). For modulated signal genera- 
tor models, logarithmic AM and pulse moduJators are in- 
serted between the divider output and the amplifier input. 
Tlie -55-dBe harmonic requirement inspired placement of 
filters at the end of the signal chain, easing the linearity 
constraint on the circuit blocks preceding the rdiers. 

To minimize the impact on tlie cost of the l-GHz-to-20-Gnz 
base model a modular design approach weis taken. The low- 
batid system consists of self-t ontmned CVV, mtKlulation, and 
directional bridge detector |>rinted ciitniit boards. I^^veling 
is accomphshed by ALC detection and drix e signals with 
characteristics similar to the microwave system, allowing 
comiTion use of the ALC circuits. This results in a system to 
which either a CW or a modulated frequency extension can 
be added widiout alTecting Iht^ l-GHz-to-20-GHz band. 

Dividers. The divider block consists of a through path for the 
50Q-MHz-to-l-0Hz signal from the microwave output nuKlule 
microcircuit and six cascaded di\ide-by-2 stages to develop 

the full iO-MHz-to-1-GHz band. A broadband Limiting ampli- 
fier is used to sum all seven octaves of divider outputs. The 
limit er's output is a 0-dBm square wave with good match. 
Power level at this point is relatively independent of divider 
drive levels. Because of the perfonnaiK-e lintitations of the 
dividers above 300 UBz iind the finite bandwidth of the lim- 
Iter, second harmonics are as high as -12 dBc. Third har- 
monics reach the -9.5 dBc level predicted by analysis of a 
square wave. 

Output Afnplifier One output amplifier covers the entire 
10-MHz-to-l-GlIz band. It consists of four cascaded gain 
stages with a p-i-n thode modulator between the flrsl two 
stages. The 25-dB'gain amplifier pro\ides a minirutim power 
of +24 dBni. A 40-dB-dyn am ic- range p-i-n diode modulator is 
used for AL£. For a stable ALC loop bandwidth over all 
power levels, a constant dB/volt transfer hmction is desu-ed. 
A shaped exponential current driver ensures a 3KlB/vtjlt drive 
characteristic that closely matches that of the microwave 

24 April IW^i Hewlett-Packard Journal 

)Copr. 1949-1998 Hewlett-Packard Co. 

Gain Stages 

lOto 1000 MHz 
dBm from 


10 to f 000 MHz 


10 Pulse Modulator 

il i 1 


i_ -VW u 

Log AM in 




' -i 

Current Driver 

Fig. 17. Low- band iDgarithimc AM modulatpr. 

Harmonic Filters, The low-band switched low-pass filter net- 
work covers t\^'^o decades from 10 MHz lo 1000 MHz. Imple- 
mented entirely as a lumped -element design with surface 
moimt components for compact size^ the network consists 
of 14 low-pass filters, tliree liigh-pass filters, the p-i-n ihode 
switches, aiid drivers to select the switches. The low-pass 
filters are spaced two per octave, providing 45 dB of second- 
hannonic rejection at the low end of the band and greater 
than 55 dB of tJiird-harmonk' rejection. Stop-band spurious 
responses are lower than -50 dBc Ifnotigh 2 GIIz to suppress 
the very rich harmonic specTJ^un of the dividers. 

All filters are seventh-order elliptic designs. Elliptic filters 
have the very steep transition band required for second- 
harmonic rejection by virtue of t r:insniission zeros in the 
stop band. 

The network is separated into three frequency bands, each 
with an ini>iit higli-pass filter to eUminate lower-frequency 
video coniiM>rients generated by the pulse modulator. Two 
filters covering 500 MH^ to 1000 Mllz are grouped together 
as one band to nuniniize insertion loss by keeping path 
lengths short, Tiie six fikers that span (34 MHz to 500 MH55 
serve double duty as liarrnonic filters for this range and as 
postfilters for the remaining six lO-MHz-to-64-MIlz low-pass 
filters. The filters have stop -band *ipurious resonances pri- 
niaiily because of the self- resonance of tire inductors usefl. 
For the tow€*r-frequency bank of filters these occur below 
the 1000-MHz system bajid width. High-order divider har- 
monics would degrade the -55-dEk" harmonic performance 
should tJiey fall on a stop-band spurious resi>onse. All sig- 
nals in the 10-Mtlz-to -04-MHz filter bank are subsequently 
routed tlirough a niivr in the 64-MHz-to-500-MHz iiank to 
suppress tlie spurious responses. For example, when the 
32-Mtiz filter is selected, tlie signal is further filtered by the 
256-MHz low-pass filler Spurious resonances of the remain- 
der of the filters are above 1000 MHz, where die gain roll-off 
of t lie output amplifier effectively reduces the high-fre<iuenLy 
harmonic content of the dividers. 

Long-iifetinie surfact* nioutit p-i-n diodes are used in all low- 
frequency filter paths lo preveju. distortion at higher p(jwer 

levels. The insertion loss of the network is typically S.5 dB. 
The network occupies a 3,5-by-4-5-inch area. 

Antpiftude Modylation. The low-band logarithmic aniphtude 
modulator is a broadband ICKMHz-to- 1000-MHz design. It is 
used ^vith an open ALC loop, in the hold position of the 
tTBck-and-hold mode. This avokis reduction of modulation 
bandwidth during simultaneous pulse modulation and AM. a 
limitation of pre\ious ALC systems. Also, AM depth is not 
restricted to the floor of the level detector. Since there are 
separate modulators for AM and ALC. the full 60-dB AM 
range is available at all power levels. However without ALC 
feedback to correct for inaccuracies or drift, the modulator 
mu5t exhibit constant drive sensitivity and fiat frequency 
response at ail attenuation levels. 

The modulator is a three-stage differential amplifier capable 
of 75-dB dynamic riuige at 1000 MHz (Fig, 17), Each stage 
consists of two cross-coupled differential pairs. Cross cou- 
pling results in a transfer characteristic that is the gaki dif- 
ference of each pair Gain is controlled by varying the differ- 
ence cLinent m tiie emitters of the dLfferent iai pairs. Mhumnm 
gain occurs when both pairs are driven at exactly the same 
current level, the signal at one coOector canceling tLe signal 
from the other 

The first stage (Fig. 18) is always in the Umiting mode, driven 
at a high RF level. The output signal is independent of the 
10-MHz lo-100t3-Mliz level and is equcil to ImodRft the differ- 
ence current of the tw^o pairs times the collector resistance. 
At low attenuation levels this signal is enough to fully switch 
stages 2 and 3. The final output is again the difference cur- 
rent, Imo^h inl<> the load resistimce R^* As attenuation is m- 
creased, I,,!,,,] is reduced. Eventually the signal from the fu-st 
stage is too small to fully swjtcti stage 2 and stage 2 caimot 
fully drive stage 3. Tlie gain of these outinit stages Ls now^ 
dependent on the drive levels of the previous stage as wtH 
as the difference current, ImiMh ^t tlie differential emitters. 

When the output signal is plotted as a fmtction of 1,^, j<3 ^1^ ^ 
logarithmic scale, gain is seen to vmy from 20 dB per decade 
change of ly^^,,^\ at low attentjat ion levels to 60 dB per decade 
change of I^kk! at higli attenuation levels. Genemting Imod 
from an exponential current source aiul then sliapmg tlie 
input to the exponential or result.s in a -10-dB/volt modulation 
input ch^iracteristic (Fig. 19). 

A minimum current, Ibias, is always run through both sides 
of t he differential jjairs to keep the transistors operating at a 
liigh gain-bandwidth point. This prevents the modiilator fre- 
quency response from changing when the modulator drive is 
changed. Temperature stability is inherent because the stage 
gain is the difference between tlte 1 wo monolithic differential 
pairs, which tend to drift at the same rate* 

Pulse Modulation. The 10-to-K)00-MHz pulse modulator is 
composed i>f iwo single-pole, doublt^-throw GciAs switches. 
On-off ratios greater thftn 90 dB aie af4neved wilh just two 
devices. An interesting fealure (if this modulator is Ihe 
thiee-speed variable-rise-time control. TliLs feature is neces- 
sary because tlie swttclied low-ptiss filter network follows 
all of the modulation. If the I^F rise lime is too fast going 
into a filter, the nut(>ut r>f the filler shows an excessive 
H^mount of ringing m\d (overshoot. Hie variable F^F rise time 
is aclueved by low-pass lUteritig lite complementary control 

April mm Mpwlpff-PHckard Joumul 25 

)Copr. 1949-1998 Hewlett-Packard Co. 




' I 

1— "- 

» - II 


Id 20 mA ^ 

V V 


Peak to Peak: 

Fig. 18, 1.o^ahttiftdc AM modular 
tor differential gain stage. 

voltage inputs of fho GaAs switches. Passive RC filters art* 
used, with an analog switching netwcak to select oae of 
three set5 of filters. The three rise times coiTespond tL> three 
frequency bands: 10 to 64 MHz, 04 to 5()0 MMz. ^oTd 500 io 
1000 MHz. 

Power Leveling 

The automatic level control (ALC.) system is a feedbiu-k loop 
that allows precise control of ifie nii(Towave output power 
level over the signal generator's full ou(put power range 
(from maximum power lo -90 dBm) and frequency range 
(0.01 to 20 GHz). Tlie main components of the ALC system 
are shown in Fig. 20. The microwave output power is 
sampled by the microwave coupler and detected by the 
diode sensing element. Tlie diode transfer function is highly 
nonlinear and varies significantly with temperature. How- 
ever, over a laige part of its dynaniic (operating) range, (he 
detector's dc voltage output changes by approximately a 
decade for a 10-dB change in microwave input power. If this 
detector output voltage is logaiithmically converted, the 
overall transfer function of the detector and the logarithmic 




i = OV 
= 1V 




= ZV 


= 3V 


= 4V 





= 6V 

1 1 i 


1 \ 

-90 n 

— H 1 \ 1 

Frequency jMHz) 


amplifier is approximately a constant. At 25°C this constant 
varies from 4 to 6 mV per dB of input power change. 

Traditionally, logarithmic amplifiers have been used at the 
outputs of microwave detectors to compensate for the non- 
linear diode transfer fmiclion. The transfer function of the 
microwave amplifier gain as a fiuiction of gain control volt- 
age complenienis that of the detector and log ajnplifier and 
is inslruniental in the detennmation of the system loop trans- 
ler function and the controJ system hand width. The gain of 
the uiit^owave amplifier can be a4justed over approximately 
a 35-dB range by applying a control voltage to the second- 
gate conti'ol hne. This increases the hannonic distortion 
generated by the imiplifier, especially near the device pinch- 
off voltage, but the hannonics are adequately filtered before 
entering the microwave couijler mui therefore have muumal 
effect on the level accuracy. 

[continued on page 2S| 

Mi cm wave 




Microwave Coupler 













Fig. 19. Frequency response of the log^iriil:iniic AM niodiiiator, 

Fig. 20. Aijsctmatic'levx: 

I liiop- 

26 April 1993 HewlfttPatkcird Joimial 

)Copr. 1949-1998 Hewlett-Packard Co. 

Internal Pulse Generator 

This secTnan describes the internal pujse modylauon source in ttie HP 83732A 
microwave Sfgnal generator The pulse generator is difiially ba^d. aitd is impfe 
menied lo a programmable gate array. Putse width, pfulse repetrtion interval and 
pytse delay can be independentJy controlled, 

The pulse generator can operate in fm diffefem modes; exteftial putse mcnfe, 
mtefnal pulse im>de. triggered pijjse mode, pulse doublet mode, apd pled pulse 

Extfirnal Pulse Mode 

in exifiFnal pulse mode the puise gefreratDr simply passes a TTl-level input signal 
fFflm ihe pyise/rngger input to drive the puJse modutator. The input pofarrty can be 
inverted Thi? mput signal is buffered ar>d passed orr to the video output. 

Internal Pulse Mode 

In internal pulse mode the pulse generator provides TTl-leval signals to drive the 
pulse modulator of the HP 83732A and the sync and video outputs on the front 

panel. Three parameters can be controlfed from the keyboard or through HP-IB 
[IEEE 488, 1 EC 625 1 commands. These are the pulse repetition intervaL the pulse 
width, and the delay from sync to video The sync output pulse width is a fixed 
50 ns. while the video output pulse width is programmable. The f!f output pulse 
width is the same as the video output minus RF pulse compression. Both the sync 
and video outputs have a nominal 50-ohm output impedance They provide +5 
volts into high impedance and greater than +2 5 volts into a 50-ohm load In this 
mode, "negative delay" is possible |see below], 

Triggered Pulse Mode 

In triggered pulse mode the pulse generator provides the same TTL-level signals 
as m internal pulse mode. However, the puJse/tngger connector on the front panel 
is used as a trigger input This externally supplied trigger signal provides the pulse 
repetEtmn interval. It is rising-edge tnggererf from a pulse greater than 2& ns wide 
Only the pulse width and delay parameters are variahfe. TTie sync output is gener- 
ated at a fi)(ed minimum time delay fmm the puise/irigger input The pulse gener- 
ator rejects tnggers during the middle of a cycle. Thus, the pulse generator can 
divide an external trigger source in this mode. 

f^ufse Doubfet Mode 

In pulse doublet mode the pulse generator operates in the same manner as in 
triggered pulse mode, but wiEh arfditmnal capability The external trigger signal is 
also passed through to the pulse modulator as in externai pulse mode. Tlius, it is 
possible to get two pulses out for each input pulse. The first is |ust the external 
pulse mode output, while the second is controlled by the delay and pulse width 
settings for triggered putse mode. If the two pulses overlap, then lust one large 



D — 
Sync Out 





fuls« Flep«trtiDn Interval 


Video Begin 1 Pulse Dfilay) 

Pulse Width 

Viiieti Enft 

Fifl. Z Internal ptjise generator timing lefatiDnships, 

pulse results, with the leading edge determtned by the external irlput signal and 

the trafling edge determined by the pulse generator. 

Gated Pulse Mode 

In gated pulse mode the pulse ge iterator responds to the external input in a level- 
seositive manner. While the external input is high, the pulse generator free-runs 
as in internal pulse mode. If the e!<ternal input is low, no pulses are generated. 
The pulse generator triggers on the rising edge of the external input, and always 
outputs complete pulses. Only the pulse width and the pulse repetition inten^l 
are variable. 





^1. HP B3732Asi9n3E generator mtemar 

April 19i^;^ Hpwlt>r.r-Pa(t<Hr(l JfuiniiJ 27 

)Copr. 1949-1998 Hewlett-Packard Co. 


The pulse generator is based on a single-counter design Timing nl width, rate, 
and delay are aJI determined from one Z4-bi1 up-counter Fig. 1 shows the basic 
•architecture. The counter counts up from zero to lN-1 ). giving a total count length 
of M When the count vb\ub matches the control word, a pulse is generated that 
synchronously resets the counter to zero and the cycle starts over. The reset pulse 
is also the sync output pulse, marking time zero of the cycle. 

There are two other registered comparators. One marks the beginnmg of the video 
puTse and the other marks the end The control words are 24^bEt video begin and 
video end inputs. A small set -reset state machine converts ttiese pulses into the 
actual video output puise. Fig. 2 shows the details Video begin and video end 
signals occurring simultaneously are defined as a reset signal, making a zero 
pulse width possible. Also, negative delay from the sync output to the video out- 
put IS possible because of the arbitrary placement of the video begin and vtdeo 
end pulses. 

The entire pulse generator is contained in one XiJinx XC3030 freld-prognammahle 
gate array. An BB-bit senal interface is mcluded in the gate array to allow load- 
ing all of the necessary pulse generator control data from the main instrument 
micfopfocessor. The pulse generator ^s clocked at 40 MHz. so all programmable 
parameters have 25-ris resolution 

This design is approximately equivalent to 25 to 30 SSI/MSI standard parts 

Dougfas A. Larsnn 
Development Engineer 
Stanford Park Division 

As shown in Fig, 21, the transfer function of the lirave ling- 
wave anxplifier output power as a function of control voltage 
is approximalely linear m tlB/volt over most of the output 
afljustment range. The rest of the components in the feed- 
back loop are Imeai' in volts/voh (integrator, ntierowave 
filters, cables, etc.). Therefore, if the cascade of linear 
components has gain A. the loop gain w^ill be approximately 

Once the loop gain is set, tJie control loop bandwidth can be 
set by choosing die RC values of the integrator Changes in 
loop gain will directly affect loop bai\d width. Since the de- 
tector transfer function changes as the diode is operated at 
higher power levels and the traveling- wave amplifier gain 
control saturates at lugher control line voltages^ there is a 
decrease in loop gain at high vernier levels. This iti turn 
causes a corresponding decrease in loop bandwidth. The 



Fr«qtiencv in GHz 



S 10 

£. -03 A 







5 1Q 

^ ^ \ \— 

f H \ \ \ 1 \ 

-3j0 -23 -^2.0 

-1.5 -l.ffl -0,5 0.0 0.5 
Control VollagB 1 volts) 

1.0 1J U 

Fig. 21. Microwave (traveling-wave) amplilier output power a.*i a 
function of control voltage. 

loop bandwidth is least at high frequencies and high power 
levels. Tlie loop baJidmdlli is greatest at lower frequencies 
and low vernier levels. The integrator pole was chosen so 
tbat amplitude level switching time is short enough at the 
minimum loop bandwidth, loop peaking is minimized, and 
loop stabiUty Ls ensured at the maximum loop bandwidth. 

Tile integrator provides the dominant pole in the system antl 
the next closest pole is from die log amplifien As the detec- 
tor voltage decreases, tlie log amp li her gairi increases and 
its pole decreases in frequency. A hmiter on the log amplifier 
gain at low input levels establishes the niininmtn pole fre- 
quency This prevents loop instabilities during transients in 
which no microwave signal is present at the detector input. 
The next pole is set at lOD kHz on the traveling-wave ampli- 
fier second gate control line. This reduces noise outside the 
ALC loop bantl width. 

Tlie dynamic characteristics of the loop have been reviewed 
and the need for the log amplifier in the feedback path lias 
been discussed. TJie log amplifier output voltage ¥„ is: 


There are two temperature dependent terms: V^, which var- 
ies linearly with temperature, and a less predictable parame- 
ter, Igs^j. 1(^11 ajid Vi are parameters of the logging transistor. 
Statically, incorjj oration of the log amplifier in the feedback 
path presents a problem and the nonJinear and thermal char- 
acterislics of the diode need to be compensated. Histori- 
cally, tliese problems have been overcome througb exten- 
sive characterization of diodes and log amplifier shaping 
techniques. Once data has been acquired on a diode's char- 
act ens tiers, temperature compensation is apphed to the ref- 
erence path of the integrator. Tliis metliod is inherently less 
ac'curate because of tJie assumption that ail diodes have 
identical characteristics. The duiil log leveling loop circum- 
vents botli the tliennal ar\d the nonlinearity problems. The 
effect of the duaJ logging transistor is that the error tentis 
associated with V^ and l^^ are ratioed out. The reference 
detector m thermal contact wi\l\ the feedback diode has a 
similar effect: the nonlmearities and tliermal variations of 
the diodes are also ratioed out- 

The input to die reference detector is a 1-MHz smusoidal 
signal. Its level can be precisely controlled with a DAC £uid 
it exhibits excellent temperature stability. Thus, given die 
symmetry of the reference path to the feedback path, the 
coupled microwave output power will be at^usted by the 
action of die servo loop to i>e iflentically equal to the power 
of tive reference. All d>i\amic enors of the loop are calibrated 
out with the vernier calibration algorithm. In this aigorilbm. 
the DAC is stepped and the instrumeni <nnt)[ii jjovver is re- 
corded. Tlien a cnne Ls fit to the pairs of points, gi^lng pt^wer 
out as a fimction of DAC tunnber. Thus, for any desu-ed out- 
put power, the required DAC value can be computed. This 
eliminates the need for adjusting operational amplifier offset 
voltages and compensates for slight differences in detector 

The most significant remaining sources of error within the 
feedback system are differential thermal characteristics m 
the detector and logging transistor pairs. The temperature 
drift caused by these effects is less than +f). 15 dB over the 
operating range of 0*^C to b^%\ The largest sources of error 

2S April h)93 Hewlett-Packard Journal 

)Copr. 1949-1998 Hewlett-Packard Co. 





¥ -3.7- 



I -3 S 




H 1 

^W.4 - 






Frequency jGHzj 

Fig. 22. Lt^vel accuracy of Uie HP 8370 and 70341] Series signal 

Bie changes in conduttor losses of components outside the 
feedback loop, such as the cables and the step alleniialor. 
This accounts ibr an additional ±0.25 dB of the level accuracy 
error budget. 

A frequency flatness c^Uiratiofi digital correction table is 
generated to compensate for component losses outside the 
leveling loop and correct the frequency unOatness of the 
microwave coupler, thereby relaxing the design constraints 
on the coupler. HPs proprietary^ planar doped barrier diodes 
are instrmixental in achie\ing the tight le^^el accuracy speci- 
fications over the vernier operating range (see Fig. 22). I'n- 
bke their Schottk>' diode eounietparts, planar doped barrier 
diodes have consisteni frequency flatness independent of 
operating power leveL 

Ac kn o w] edgm e n ts 

hi any successful project there are many people who contrit>- 
ute to the overall success. Thanks to Soojin Choi for devel- 
oping the bondabie gold-on-Duroid-suhslrate process and 
ensuring the design was nianufaciurable during the design 
proceas, to Eddie Plantiilas for de\'elopnient of the test sys- 
tem, to Jolin Duran for endless hours of testing of the envi- 
rotmiental and prototype units, to Harrell Huckeba for partial 
development of the modulation module, to Yvonne \'ieira for 
her skill in building the t>readboai'ds ^md protot>pes, to Ed 
Cirimelle for flawless housing designs, to Marlene Hartigan 
for keeping us organized in tracking our defects and solu- 
tions, to Jim Logic for setting up the fab parts atid helping us 
out of the polyiron cracking problems, to the team at the 
Microwave Technology Division — Morgan Culver, Gene 
Burdick, Ted Shimkowskt and Sig Jolmsen — for development 
of the ceramic hermetic traveling-wave amplifier package, to 
Orrin BaJsden and Al Bates for keeping the material straight, 
and t.o Mark Johnston for coding all the algorithms and 
Juggling an incredible amount of inputs. 


1. MK. Koenig, "^A High-Speed Micrnwave Pulse Modulator," 
HmileU-FackaM Journal Vol. 42. no. 2, April IMfU, pp. 'M4i(x 

Apri 1 1 m \l\p wk't T "Prir kim\ ,lou mal 29 

)Copr. 1949-1998 Hewlett-Packard Co. 

Concurrent Signal Generator 
Engineering and Manufacturing 

Production tests were developed early enough to be used for design 
characterization. Several new production processes were developed. The 
project had a design-for-assembly philosophy, an integrated assembly and 
pretest strategy, online videoimage production procedures, and a 
networked computing test environment. 

by Christopher J, Bostak, Camala S. Kolseth, and Kevin G. Smith 

The project team for the HP 8370 and 70340 Series synthe- 
sized signal generators attempted to develop the requisite 
manufacturing processes in parallel with the product design. 
Key manufacturing and R&D personnel were collocated and 
iiinctions were blurred as necessary to accomplish this ab- 
jective. The lalj pilot run used the j>lanned manufacturing 
processes and personnel as sm>n as possible. By developing 
many of the prodtiction processes early, we were able to 
leverage tlie pmduction tests to pertbmi aiiditioniil design 
characterization. Several new processes were developed to 
accomplish tlie overall objectives of quality, efficiency, and 
flexibility for a mixed-model, multiple^ption production line. 
In tlus article, we describe the design-for-assembly pliiloso- 
phy, the integrated iissembly iuid pretest strategy, the imple- 
mentation of online video-image production procedures, ;mcl 
the networked coniput ing lest environment. 

Design for Manufacturability 

A number of design features facditate the mixed-model 
i^roductlon mode. The niierocircuit chain is integrated and 
maintains tJie same form fac tor and connector k^cadons in 
modulated and unmodulated instnunents. Tlie housings and 
covers are common parts. With the excci^tion of the front 
panel, all the sheet-metal and chassis parts, hic hiding tlie 
subpanel and the rear panel, are identical across the fanuJy. 
Tlie form factor of the circuit boards allows mounting in 
both the Mo< hilar M eiisu re me nt System (MMS) ar;d the IIP 
System U ent^losures. The interconnect strateg>^ allows the 
simple addition of turi her enhancements by including 
excess capacity. 

The design-for-assembly iihiJosophy adopted at the beginning 
of the project is evident in the final design. Tlie re are several 
examples of part coimt reductions. Tlie main deck assembly 
for the IIP 8370 Series is a prime example, bistead of being 
screwed together on the assembly line, liirge portions of die 
chassis are riveted together at die sheet -n^etal facility. This 
reduces inventory and Jtssembly costs. It also improves qual- 
ity by guaranteeing that all the parts fit togettier. An error in 
fabrication is discovered sooner, and less scrap is produced. 

Tlie main deck a^ssemhly I nc hides the main deck, die tang 
deck, the rear panel, two side stmts, the fan cover, the oscil- 
lator bracket, the rear frame, and some hardware. Instead of 
pressing in capt ive inserts and screwing the parts together, 

these parts are rive led at the fabrication site, saving an 
estimated 4^4 parts in final itssembly Another ptut re<:luction 
is realized by attaching the display UF shield to the subpttnel 
by a semipierce method, A hinged board service strategy 
was reengineered eiirly in the development to elimhiate a 
few tiozen parts and replace tJieiii with one part.. 

The tang deck includes sheet-metal features that hold the 
boards in their service positions (see Fig, 1). This design 
chiinge was tlirectly driven by early jiroduct ion engineering 
involvement. In addition to part savings, the assembly is 
rnueh sin'^i>lified. To a great extent, the unit assembles from 
the top down m\d assembly reversals are minimized. 

Assembly and Pretest 

The HP 8370 and HP 70:340 Series microwave signal genera- 
tors are tussenibled and tested using a motieni "layered" man- 
ufactming approacii coml>irdng \ideo-iniage-aided instruc- 
tions and in-situ testing by die assemblers. The traditional 
approach h^LS t)ecii to assemble and test the various boards 
and modules separately with dedittated fixtures and then 
bring them all together to be tested as a final product. This 

Fig, t, HP 83731 A showing ttie tang deck with board In service 

30 April 1 £193 HGwlett-Packard Jo tinia] 

)Copr. 1949-1998 Hewlett-Packard Co. 


Ref/LO Pretests 

Scan/PuJse Preresi 


Micfoprocess&f Pretesls 

HP a370'SpeGHic HP 7034{^Sp«cHic 
Power* Fan Preiests 

Mi(.rcifirDi^«:kAor A»««mlitY 

Powcf. Fails. Caiil&i 

Mil (II Odcb A«9Jnntil| 

MkroptiKefsot ^bseiirtil^ 

pitrwer Strpply Pretest 

Ptiwtf SSpplyTFati Asseitkbly 

Genrratx^r Ba%c 

A^^mblr Rtinr PAneJ 

ALC Pretests 

VJG Orrver Pretests 

Mruowsve Deck 

¥0 iDOp/FM Pretesl 

Oflset/YO Pretests 

Fig- 2, Matiuracturing process flow, sh(Hs1n^ intt?grate<l assembly aiid pretest steps. 

method can often lead to cost ly instmment-level troiible- 
siiooting and rework. Also, the assembly iind teat fimrtions 
have hifitorically been executed by sepai'ate personnel. 

By testing the signal generator layer by layer (siibasseii^bly 
upon subassembly) we reveal as many potential failures as 
poi^sible a( (heir earliest aiui hence least costly point:s of 
opportunity. The tenn pretest, as tised m tJiis article, sijnply 
refers to testing an assembly short of the finishefl product 
and applying interitn test criteria We tirgue that tJie success- 
ful impleinetitation of this approach, integrated with robust 
product design, will prove advauiage<jus to conipimies with 
a highly diverse product mix artd with medium to high 
production volumes. 

In addition to early problem discovery, pretesting duritig 
assembly offers a lumiber of other benefits. First, this 
method minimizes the cost of buildijig, document iog. mid 
handling test fixtures, jigs, adapters, m\i] the like. Ex<'ept for 
the test rat ks, iiiiy "fixttuijig" should be built intti tlie product 
itself. Second, each assembly is tested in the actual itistni- 
ment enviromnent. Tli ere fore, the assembly is subject e<i to 
more retilistic component variations than by an ideal fixtiue. 
Finally, the dLscoveiy ai^d resolution of failin-es early in the 
production process helps minimize costly cycle time resulting 
from faihires in the ftnal test stage of the process. 

Approximately 23 principal assembly and pretest steps must 
be performed before the instrument is considered complete 
attd begins final testing. The actual number of steps difl'ers 
from model to model within the signal generator family. 
These steps are t^resently divided between two workstations 
or *'ells, Pretest 1 and Fret est 2, us shown in Fig. 2. fJoth tire 
essentially identical and can haniile all "pretest 1" luid 

"pretest 2" procetliures. Tliis gives the hne maximum flexibil- 
ity In Fign 2, process steps that are pretests are indicated by 
open boxes. This i>ari1l ioning largely follows the signal gen- 
erator l)iock diagranL Note that a nmnber of items sucli as 
microcircuit nwdules, printed circuit boards, and power 
supplies are assembled elsewhere and may undergo addi- 
tiotial prior screenit\g. The assentbly anti pretest process 
described here is at the instrtutient level only* 

Eacti assembly and pretest station consists of a well- 
etptipped workbench with a computer terminal anci an aftja- 
cent test equipment rack {see Fig. 3). A dedicated material 
handler ensmes that kits are available to assemblers vvhen 

Fig. *^. Assembly/pretejit workstation. 

ApHl 195*3 He wlett-Pat^kard Js mmz\ 3 1 

)Copr. 1949-1998 Hewlett-Packard Co. 


»^> 1 , 

Asseinble Front Panel 



Main Deck Assembly 



Poufr jFan ,Cbls Install 



DC Cab/Ml croproc Assy 



ET Inslal 1 at L on 



DC/Rpnl Cab, Dsc Assy 



Pouier Supply Pretest 



uProcessor pretest 



Store S/N and Options 



Ref/Lo Assembly 



Ref/Lo funct pretest 



Ref syn pretest 



Lo syn pretest 


23 Sep 1992 16:28:19 Serial Mumber: 3233A00131 


Uiier I Laps Kunn i n^ 

Fig* 4. Elxainjfle (vfipRj pxpciitivr 
menu for assembly and |jrf.?Lt^'Hl 

iif'f^fled. Barfiwaif' aiid other frpquently used parts sue stoiTd 
in easy-to- reach bins on caiiillevered amis at the fully ad- 
jiLstahle, ergononiic workstations. Eqtiipment commonality 
ensures tliat any pretest can be nm at any pretest station. 

A cotnftton operator interface is shared between the pretest 
station and other process workstations. Tltis interface is 
provided by an HP 9000 Series 300 computer with a color 
graphics display rtmning the HP-UX'f' operating system, the 
X Window System, HP BASIC'/l'X, and a test executive that 
generates menus. Tliere is tremendous nexibility in this 
scheme, Asst^mhlcrs and t>thcr test operators need very little 
additional training to be(*ome inunediately produr!i%'e on 
new workstations in I he line. 

Once an assembler Jogs onto the pretest station terminal , 
the \ide(j display presents Ihe menus Cor producT, station, 
and proeednre seleclitMi, When the ai)]>ropriate instrmneni 
tyjie and station aie selected, a menu listing the stepwise 
sequence is displayed (see Fig. 4 ). Wheu a step is selected 
the test executive loads the proper assembly or test soft- 
ware and directs and prompts the operator by means of a 
series of images. 

Types of Pretests 

After an image-aided assembly procedtire has been com- 
pleted, tiie next step is often what is refen'ed to as a fimc- 
tional verification pretest. Tliis test leverages built-in test 
features and merely requires ac power and an IIP-IB (IEEE 
488, lEC 625) connection to the test rack. Functional verifi- 
cation tests use the digital and anakjg buses to detennine 
po%ver supply voltages, tlafa read back capability, miscella- 
neous analog voltages, digital flags, and so on. Jn tether 
words, is the DUT (device mirier test) minimally functional? 
Tlie principal goal of this test is to detemiine, with a Iiigh 
degree of confidence, whether the DKT hits l)een assembled 
correctly. A well -written explimation of a similai- self-test 
and analog bus strates5^ can be fotmd in reference L 

The next step is the perlbrmance pretest, which uses equip- 
ment in the test rack to detennine if the assembly is provid- 
ing oiitpuLs withm the specifications necessaiy for the next 

level of asst^mbly This step can provide in format ion tJiat die 
hmctional verification procedure cannot. Boaids are tested 
for perforniaru e criTeria such as frequency accuracy and RF 
power output. Eiich of the pretests takes approx.imateIy five 
minutes or less to execute. This is insignificant with respect 
to tnt:al process flow. 

The sy stent is intended to be simple. Each pretest provides 
pitss/fail infonnation to the operator. If the DUT fails, the 
assembler removes the last failed subassembly and passes it 
to (he defect elimination station (Fig. 'j] for troublesbootinj^, 
A knowivgood module from a pretest buffer is substituted 
Ibr the failed module so that the unit can ctjnl inue with mini- 
mal delay to tiie next assembly procc^ss. Consecutive faihues 
on the retried pretest require the operator to ask the defect 
eliminadon teehiucian for assistance. The defect elimination 
station has a more extensive diagnostic test station and a 
knowii-good instrument, which assist the technicians in iso- 
lating failures to the component level. Once the failure 
cause is determined, the module is reworked, if possiblej 

Fig. 5. Pre n?si/di.! feci elinmialiuii ratik 

32 A| >n I I J (9;H I e w 1 ot T F^i [ ■ k:mt ,f r h im aj 

)Copr. 1949-1998 Hewlett-Packard Co. 

and delivered to a buffer of known-good modules for fiiture 
use in the assembly /pretest process. 

Since in this sfiieme tlie asseinhlers are responsible for 
screening tlieir own assemblies, the assemblers must be 
trained adequate ^v to a relatively higher level of <*otnpe- 
tenee, iJiat of iissenibler/pretester, Thej' must be comfort- 
able inf eraeling with a \ideo terminal and in handling live 
equipment . Additionally, there are some limiiations on the 
pretests ihemseh'es. These are primarily related to speed 
and persomiel skill set. First, the l^^neal manufacturing pro- 
cess requires that board and module pretests should be 
short in duralion for higher total tlu^oughput. Second, they 
should be high-\'alue tests ihat do not reciuire too much in- 
terpretation. Relatively higli-skill-level operations such as 
acyusting potei^tiotneiers and interpreting os<illciSCOi}e traces 
generally do not lend themselves to this approach. This may 
exclude phase noise or switching speed tests. h>r example. 
Pretests also may not catch heat related problems cjr intf^- 
mittent failures because of the relatively shon periods of 
instrument operation. 

Defeii elimumtiou troubleshooting tests are more detailed 
and extensive than pretests, and pretests ui turn are a super 
set of tlie functional verification tests. Each bo;ml has a 
number of analog, digital, and RF test poijits available to ihe 
defect elimination technician ihi troubleshooting ui addition 
to the (jtutputs tested in pretest. The microprocessor board 
p erf onus its own low- level self- test on power- up, checking 
powt^r, ELAJVls, clock, and s(j on, aJul iadicales test status liy 
means of on-board LEDs. an especially useful feature. 

Success Facturs 

It has been estimated that at least 7tMj of a product s life 
cycle cost is determined in the design stage. Hence the mod- 
em emphcLsis on design for maniiraclurability and design for 
testability as keys to competitive adviintage.-^ 11ic adoption 
of a test-as-you-build approach naturally iniposes its own 
stjeciHc <'t)ns] derations (see "A Design f*jr MtUtufacturabiJ- 
ity. Design for Testability t'hecklist," at right). 

It should be noted that this approach benefits most from a 
project or systems enguieer t hat acts ;ts the system architect 
and oversees tlie partititm of toij-level [ iustnuueiU-level } 
specifications uUo required traceable "harcf specifications 
at the mrjdule or j)rinted t iiciiil board asst'tnbly level. This 
activity will becTmie even tntjre imt>ori.ani as finns at tempi 
to leverage designs from produtl to product and considi^r 
make -or- buy and intenial-orextenial dec i.s ions. Karly hard 
specifications imder the control of a single chief engineer 
best allow for successful concurreni design, inanulacfuring. 
and test. Experience is unqiiestionably important itt dtis 

Concntnent test develoijmenf always involves hitting a mov- 
ing Target. This is paiiitiilarly tnie in this scheme because 
sj)erifi( ation and test scotje ch<ijigcs helow the final uistru 
ment level hHve a direct impact on Ihc pnlests. BoiuxMevel 
and mo<iule-ievel specificaliojis may Lie inadequately derived 
or documented early in a progratu. There may i>e protilem 
ventioi's. Special orders and options abided later in program 
development will impact hardware ;iii<i fij luware designs. 

Ptjr a dis<*ussion of design for testability and the impoHance 
of adequate parti tionhig see reference 3, A good argument 

A Design for ManufacturabOitjv Design 
for Testability Checklist 

Some dea^gn tar fnaTiulactuiabihty and design tor testsbility issues fsquire special 
consideration when ctesigning an msirument for tfe Eayef ed assmrihly and pretest 

lectiojque described m the acco^panyjr^g amde Hece are a few examples \m&d 
on oyf expertence m working wjth this tamily of rnstrurr^nts' 
First, the mosi general cancem: Istfie inEtrumem partitiorwd eftKiJVilv, berth 
functionally and pNysacally, for layered assembly and pretest such that faufts can 
tie delected and isolated independenfly and unambiguausly'? For eKample, a 
singJe-board phase-locked loop is generally pfsferred over one distributed on 
several boards 

If using a switctiing power supply, wilt ihe power supply start up with the mini- 
mum loading presented by the lowest testable instrument assembly^ If not. then 
an imarim load frxture will be required 

* Can the instrument be operated as necessary fe g , via the HP-IB} if the front panel 
IS not present? Same processes may find liiis desirable for assemblability or cos- 
metic reasons. Don't forget the on/oft power switch 
Are all shared irtilittes fdigitai buses, power, and analog buses) capable of operat- 
ing with the mstrumeni in all permutations of assembly^ This is important not |ust 
for the standard assembly sequence, but for possible service, repair, and reworlt 
Consider circuit board loading, failed component problems, possible signal sneak 
paths, cabling, and so on 

■' Are test outputs designed, and the instrument partitfoned. to be compatible with 
the typrcal 50-ohm mpul impedance ol standard test equipment'? Can oscilJo- 
scopes, analyzers, and other gear be ser for high impedance if necessary (e.g., 
1 meg ah m)^ If noi test outputs should be adjusted tor the correct impedance, 
polarity, coupiing, power levels, and so on, or fixturmt} may Oe required 
Has the irnpaci of calibration procedures Oeen mcluded in the design of preterits 
and borlt-in test firmware code^ For example, if the VIG oscillators are not 
calfbrated. the YIG oscillator loop may not locJt 

- If an assembler must operate flyrng-fead osciJIoscope probes on the board, are 
there adjacent and obvious test points [both signal and ground)? As a matter of 
routine, assemblers should not have to probe components, attach ground dips to 
the chassis, or perform SFmilar tasks 

Does the instrument design allow for additional ophons without requiring access 
to previous subassemblies'' For example, are micropiDCessor board DIP switches 
readily accessible' In other woids. consider ihe impact ol hkely future options on 
ihe instrument and its assembly and test early in the design Don 'I forget the 
impact of options on the organization and design of the test soltware. 
Have ali waimup-related mm been eliminated oi minimized? Assemblers must tiEfn 
units off to work on them between tests fherefore, tests sensitive to components 
or arcuits requiring even ten minutes of warmup lime are not good r;andiri9tes for 

Does the functionality of a unit or assembly vary duiirsg the manufacturing process? 
For example, thermal and electromagnetic effects rnay be rt\ore variable with the 
covers off 

Finally, since the instfument itself is the ultimate test bed. are one or more pfoto- 
types scheduled and budgeted in the project for concufrent test deveiopment' 

Un* the grrierai r(*tHejMs of rolmst design and specificatioii 
tolemiites is presets [ed m i iTrTonce 4, 

Networked ('Omputingand Test Environtitent 

If pretpsts cuukl acrnrately tesi all nrtlu; i^arajneters Ihal 
detotniine the porruniiajict' unite jjisUTjjiieiit, iiti fvir't.her 
testing wtjuld bv necessaiy. However, in roinplex ituslni- 
nienls like the IIP 81^70 cUid 70^14(1 Series synthesizers, there 
are trxj ititmy variables ;aid ho^uri infezatlions to gujiiniilet^ 
sysleiii <)|>eralioji lii^iseti U|!un [attest results, Tliert^ft^re. 
final test verifies that tJie etaiiplete anil rf>inplies with ihe 
warran led speei fi eatj ( m s . 

P'or maiiy years, the test strategy for mamdiKluiing high- 
perfcjiitiaiKT tiiiert)wave fre^itteiuy synlhesizei>i hhts lollimetl 

April m:^ Ik'wlvU V:irkim\ .hnjnial 33 

)Copr. 1949-1998 Hewlett-Packard Co. 

a traditional ni<*thoclology. Each inslmnient si^ecification is 
tested. The tests are gioupetl by funt'tioiT or by iise of eoin- 
mon equipment in test stations. A tesi station contains sev- 
eral pieces of measuiiiig equipment whtcb are operated 
either majiualiy or by a compuler. Eacii computer and 
system Ls independent of tlie other computers and station^?. 

This approach, while conceptually simple, leads to several 
pn:>bl(^ms. Implicit in manual tests is operator intervention 
and sometimes interpretatit>n of the data. Ini^onsistent re- 
suits occur under these conditions. Even withaui operator 
in ten-mention and interpretation, production line capacity 
needs cmi dictate inuUiple identical test slatiotis. A topical 
production line migfn have ten or more different test sta- 
tions, each operating intiependently. Pi'ol)leins can arise 
when it is necessary' to ujjdate some tjf the test procedures 
or analyze data that is on several systems. There have been 
solutions in the past that have corrected some of these defi- 
ciencies. Older computer networking schemes like Hewlett- 
Packard's Shai'ed Resource Management (SRM) sofrwaj-e 
and hardwaie allowed com[>utet"S running HP's BASICAVS 
software to comnnniicate on a mdimentaiy level and share 
files and f)rii\teis. To analyze data, people wrote their own 
software to calculate means, standard deviations, and oUier 
statistical process control information. Until recently, there 
were insLifficient products to allow enough contiol and inte- 
gration of the test process to make it economically feiisible 
to use it on a production line with a capacity on the order of 
50 to 250 units per month. 

in designing tJie lest systems and the surroimding compuler 
systems for tlie HP 8370 and 70340 Series synthesizes, we 

had several important goals. First, in keepmg with our de- 
sign team's goal (jf roncunent engineering, tiie test systems 
needed to aid the R&D engineers in the characterization of 
the product. Second, while aiding the RiftD engineers was 
impoiiant, the systems needed to be easy to use for people 
with widely varying skiU levels. Third, the test systems 
needed lo he organized such that the test times at all of the 
stations were approximately equal for an eftlcient jiipehning 
system. Fourth, ail of the test systems neeiJed to be inte- 
grated in a manner that allowed lile and prij iter sharing, ac- 
cess to the data for analysis ^ and display of digitized images. 
Last, the cost for the integration of the process was to be a 
small fraction of the test equipment cost. A production sys- 
tem with these characteristics would yield an efficient and 
organ izeil production line. 

Given the above goals, there was one choice tliat seemed 
most appropriate. The production hue for the HP 8i570 ajid 
70340 synthesizers uses a cluster of networked HP 9000 
Series 300 computers running the HP-tJX operating system. 
A diagram of the configuration is show^n in Fig. 6. A central 
server stores tlie operating system and all of tlie production 
test st)ftw*are on a disk. Each test system has its own com- 
puter tliat boots from tlie serv^er. As shown in the figure, at 
the physically remote location in the en\iromnental test lab, 
anotlier server acts as a repository for the operating system, 
while the test softw^are is linked to the maui i^roduetion 
ser\^er. This allows one lo<:^ation for the storage of both tests 
and (lata. The main server also has access to the disk that 
the image cajiture PC uses to store tlie images. In this way, 
(here is an easy transfer of the images from development to 
I he production line. 













Enviroiimentai Test Lab 



PrtMtuGtion Llfie 

DE ^ Defecl Etimmation 

Fig* 6- Computer network 

34 April 1903 Hewlett-Packard Journal 

)Copr. 1949-1998 Hewlett-Packard Co. 

Offset Yo PC Board ■ OFFSET SYNTHESIZER PRETEST, Offset'Yo PC Bd Setup 

^ Disconneci coaK cabit (9) from 13-26.5 MHz In (J105). 
Malce the followmg connect^cns: 

Ji Test Say 'TS1^ • to the Offsei'Yo PC Board t3-26,5 MHz Qitt 
IJ1) Coai Cable using a BNC^SIIC Adapter ■. 

■ Turn on the Test Bay MMS Dieplar'llaiiiframe, 
Type cQ> 10 quit from ilijs seijuence. 


[^I ■ 


Scene file no. 


Rev. 2 

Fig. 7, V'ideo iiiiHge example 
froni the offset syniheaizer 

The same lest algoritlmis riiat were used for die develop- 
ment of the product are used on the nianufacturmg line. In 
many cases, this is not the ideal approach. A better way is to 
identify a small set of chararteristncs of the product that 
accurately represent itj5 functionality, such that testing these 
parameters detennines whether the product is const meted 
correctly. If the product design is originally well-chai'act erized 
and proven, this simple tutictional test is sufficient to prove 
that it meets all specifications. In the case of the HP H73() 
and 70-340 Series synthesizers, loo many parameters are not 
completely predictahle or controllable- As a result, we test 
to the specifications threctly. This leads to a large number of 
tests and a potentially complicated test system. 

To combat this problenn, several levels of software are used 
to achieve a simple user interface. Some people are afraid 
(hat the technicians and tissembiers on a nianufarluring line 
will not be able to use the HP-l^X operating system. Using 
llPs implement al,if>n of the X Window System and running 
HP BASIC/LIX, the interfjice is not nutch different froni whal 
the technicians and assemblers have experienced in the past 
in independent stations. The amount of effort required to 
implement this interface was minimal. 

By setting a go^il for tlie tluoughput of the line, it w^as pos- 
sible to di\dde the test systems so that eat^i system tiikes 
approxunately the same amount of time to do its job. Losing 
the clustered enviromnent allows many other benefits. The 
need for a printer al each test station is otwiaied. As stated 
earher, tliere is only one place for all test and data files, which 
eases modification, revision tracking, and data retrieval. 
Potentially, the HP-liX system allows much greater flexibility 
in the use of other KjoIs, such as defect tracking systems, 
tiaia analysis programs, arul so on. Powertul statislkal and 
mathematical software trackages are available to analyz(^ the 
clatiL Once fajiuliar with the basics ofihe system, techiticitms 
iiave expaniled their knowledge by using the multitasking 
capabilities of the computers to do several tasks at once- 

The cost increase for tliis system over other solutions was 
niinimal compared to die cost of the test equipment. The 
HP-UX-based system provides fjie greatest. Oexibilit^'^ w^hOe 
saerincing Uttle of the original goals. Developing the soft- 
ware under HP-UX was a great help to the learn because it 
allowed sharing the information and software at an early 
stage and an early trial of the use of tiie HP-UX system on 
the mamifacturing line. Thus, the netw^orked computing 
environment jjrovides n\any advantages over Uie previous 
method and lays the foundation for continued process 

Online \ldeo Image Procedures 

Onlme video image procedures for assembly and j) ret est 
provide quality dr>cimientation to the a^jsemblers, help main- 
tain the integrity of the pn.Kjcdures, and minimiite paper 
drawings and dtx'vj mental ion. The procedures t^tjuibine text 
with graphics ;md are color-coded to conestjorul t.o the se- 
quence of assembly and iirelesi (see Fig. 7). The j)ro<^edures 
are presented to tlie assembler onhne by an HP 9000 Series 
300 computer w^hich also controls the test equipment for 
pretesting at each workstation. The video images are inte- 
grated into the test executive software environment, thereby 
providing a single user interface fiir both assembly and pre- 
test operations. The online Tiature of the proce<hires ensures 
that aU assemblers see the same version of the documenta- 
tion. In addition, the proc^edures have proven to be a useful 
trjiining aid and help to expethte the learning process for 
new assemblers. 

The HP 9000 HP-ILX platform was chosen because it meet^s 
the requirements for both online video image presentation 
and a well-managed tlistnbuted test strategy, hnage files are 
transferred electronically lYom the image capture develop- 
ment piattbrm (DOS-bi:ised) via the site LAN cind a dedicated 
storage drive to the HP 9000 network server on the produc- 
tion line. Tlie image files are received in TGA gniphics fonnat 

Apri 1 t0a3 Hewlett-Packard Ji xj n lal 35 

)Copr. 1949-1998 Hewlett-Packard Co. 

[mage Caj»ture Lab 

CalDF MonitoT 



Coror Printer 

Color TV 

Video Camera 

y LAN Conneclion 

Sits C»m|iuters and Storage Drives 


MMS/SI Froifuctieii Line 
N^twoik Server 

LAN Connection 


HP 9000 


Assembly and 


Fig. 8. Image c:apt.ur<' lah hardware logisti(\s. 


Final Test Final Test 

HP 9000 HP 9000 

Model 375 Model 375 

HP 9000 

Model 380 

Assembly and 


from the de\^elopnient system. A c^oiiversion utility is used to 
tiatisform tlie files to (tIF graphics fonuat for dis|)lay on the 
IIP-ITX platform. The resuJling GIF files are stored on the 
production network sen er Since assembly and pretest 
steps are combined Ihroughoui the maniifaeliiring process, 
display of all images is controlled Ibrough the inenn-driven 
test executive that rntis the pretests. 

In establishing our video image capture process, we were 
able to leverage sigtiiflcantly some earlier work fione \\\ the 
HP Spokane Division. Our hardware jjlat fonn and sofi ware 
tools minor Spokane's implemeiitation, with the addition of 
onlhie image viewing. 

The \ideo image procedures are developed offiir^e in mx 
image capture lab. Ilie lab is equipped witti an HI* Vectra 
486 compuier, a PostScript'^ color printer, a large-screen 
color monitor, a i'iyXox television set, and a liigh-resolutton 
video camera (see Fig. 8). Software tools rtuming on the HP 
Vectra 48G PC are used in the process (see Fig. 9). Picttires 
of the assemblies are taken in the lab with the frame capture 
camera. A 4M-byte video graphics adapter board accepts the 
data from ihe camera and converts it to a TGA file. It is then 
necessary to correct the aspect ratio of the captured image 
for use in a paint program. A software tool that employs a 
linear interpolation technique is used lo ac^jusl tile image !o 
the required aspect ratio. Tlie image is then callcil into live 
paint program where color modification, shading, and otJier 
techniques are used to touch up the picture. Once the 
pictures have been refined, they are accessed from an 
object-on enled development tool and combined with col- 
ored text and objet^ts to fomt a scene, or procedure. The 

entire^ sceite is rendered and saved by this software tool as a 
TGA grapliics file (in efi'ect, a snapshot of the scene). At this 
pomt. the TGA file is copied lo the image capture storage 
drive for trtmsfer to tile HP i^UOO serv er. 

The Ullage files thai are referenced in the scenes are quite 
huge ( 2 to 4 Mbytes each), and it lakes many files to niake a 
complete asseml>ly ajitl pretest procedure (the HP 70340A 
synthesizer takes ap|>roxlmate[y 70 scenes). Consequently it 
is necessaiy to at chive the files on stnne other storage 
mechanism. Again, we w^ere able to use a softw^are applica- 
tion and corresponding file-tiaining convention developed by 
the Sptikiute Division to archive the files m an organized 
manner. The software is a mouse-activated^ n i en u-d riven 
application that allows the user to specify scenes to archive 
or retrieve. Tlie stJftwiire automaticiiily verifies the file natiie, 
compresses the file, and copies the file into the correct sub- 
directory in the aichive database. Tlie archive database re- 
sides on a dedicated storage drive atid is accessed from tlie 
Vectra 48(3 via the site LAN. 

The test executiv e gave us a v chicle for providing a consis- 
tent n\eiui'driven user interface for both assentbiy and pre- 
test procedures. Extensions to the test executive were de- 
veloped to facihtate the display of graphics files. All images 
are stored in one image directory in the test executive s hier- 
archy. HP BASIC/LTX programs were added for all assembly 
or pretest steps diat invoke a utility for displaying the miages. 
hnage lookup tables provide a map for cross referencing 
model and option combinations to die correct sequence of 
images to be displayed. Assembles simply eni er the mi>del, 
options, and serial number data at the test executive menu 

36 Ap rii 1 0fl3 H(^wli^'Pa<;kaTld Journal 

)Copr. 1949-1998 Hewlett-Packard Co. 

4S& E^iroitment 


(32 Bit} 




Scene (a-6it| 


Scene and CcHnpi essed Jmages 

UMX Server 

Scane (6 IF) 


Storage Drive 


Fig* 9* linage capture Jab snftvvaro logistics, 

prompts, and the c orrect. sequence of proceduies is dis- 
played in the X Window environnit^nt. Hooks are available 
for ent**ring data by means of a bar-c*ode scanner from tJie 
serial label on the inslnrrnenrs rear panel. Tlie assembler 
advances front orte itna^e to the next for a partictilar assem- 
bly or pretest step by tappiiti^ ttie space bai-. The backspace 
key is used to return to a previous inii^^e. In the case of a 
pretest step, instnK^tions are displayed for the t est setup and 
the test drivers are automat ically Invoked front the same 
procedure when tJie assembler advances past the setup. 

Conclusions and Comments 

The synthesizer majtiifacturing process continues to undergo 
in<:rernenUil imt^rovcntent. Tlie integrated iissembly and 
pretest process has already been successful in improving 
the quality of instruments presented to final test. FaiUjres 
are being audited to see if the pretest strategy can l>e tight- 
ened reasonal>ly to tninitnize such failures. Work remains to 
fme-tune the proc^ess and extend it to other instruments 
and optioits in ttie family. 

The networked computing environment has proveti to be as 
useful and flexible as forecast. The image capture proce- 
dures have beett well-received by the asseml)Iers aitd have 
already proved useful in shortening the leanting period- Ex- 
[jerieiKT gained in this process should ejiable ils to acltieve 
greater flexibility anci use the same liite for extensions to the 
same basic instniments. 

Ac k no wledgm ents 

VJ. Bonnard organized and led the rnanufacttiring new prod- 
uct introduction project team. Steve t'tninitigham contrib- 
uted significantly to the product's design for mfUiufacturabil- 
ity. Dave Milani was tlie origirtaJ aichttect of final test, John 
West.enitan at the IIP Spokane Division established ihe 
image capture process that we were stj successfully able to 
leverage. Thanks to Paul Antdf of tlte ^Spokane Division, 
who inherited the process from John mid who prrmded us 
with tn valuable technical support during our image capture 
implemenlalion stage, to Jint Bertsch for his inputs to the 
design for ntanufacturability discrussion in this atlicle, and to 
Tint Chan for the photography for Figs, 1, 3, and 5. 


1, MJ, Seibt'l, ""Built-in Synthesized Sweeper Self-Test and Adjust- 

nu^riLs,'" Hcirfctf-Pftrkfirfi MntrnaL Vol. 42, no. 2 ^ April b)91, pp. 

1 7-2:1 

:i. [mpmping Eiigineenug Dmigtt, U.S. NRC, 1991, p. L 

G. J, Tbrino, Desigtijor Test, Van No.stranfl Reinhold, 1990. 

1. G. Taguciii and D. Clausing, ""Rohusl Quality," ffftnafd Bitmfwss 

Rvrlrw^ January -F eh niary 199(). 

HP-UX fs based on afvri is compatHjle with UNIX System Laboraiorres" UNtX' pperating system 
II also complies wHh X/Open's* XPGa, POSIX 1003.1 and SVIDZ interface specificatiar^s. 

UMJX is a r^istfired trademafk of UNIX Sysiem Labora tones Inc In the U.S.A. and other 

X/Dpgn IS a tractamtark of X/Opert Company UmitBd in the UK and other countnes. 

PostScnpt IS a registered tfademark of Adobe Systems, Inc. m the U.S.A. and uther toymnes 

)Copr. 1949-1998 Hewlett-Packard Co. 

April imm I lew]i^tt-r:U'kard JoMmal 37 

A New Generation of Microwave 

The HP 83750 family of microwave sweepers achieves a new level of 
swept frequency accuracy by being fully synthesized in all sweep modes, 
including fast analog sweeps. It also uses fundamental oscillators for 
improved signal purity. 

by Alan R. Bloom, Jason A. Chodora, and James R, Zellers 

Swepl'freqtiency naicrawave signal sources {sweepers), have been cunsklered basic equipmeni R>r ff>mp(.ineni tesi 
applications. Sweeper capabilities also satisfy many general- 
puqjose nee<ls, buili in the laboratory and in production. 

Tlie first HP niicrowave sweeper, tJie HP (t70A, employed a 
klystron oscillator, wMch was mechanically swept by means 
of a motor drive. Sweep speed t*apability was improved con- 
siderably ill the 19(jOs by the IIP 8690 Series, which employed 
m\ electrtiniciilly-tuned backward- wave oscillator (B WO). In 
I he 1970s, the HP 8620 Series achieved new levels of reliiibll- 
ity by replacing BWO inbes wilh solid-stat e VIG oscillators. 
In 1980, microprocessor control was addetl in the HP 8350 
Series sweepers^ to provide full progranimability and many 
convenient user features. 

The frefiuency accuracy of most sweepers, including those 
mentioned above, is limitefl by the microwave oscillator and 
its drive electronics. Newer synthesized sweepers, such as 
the IIP 8300 Series," achieve excellent frei]uency acciuacy 
in CW and sLepped-sweep modes. In continuous-sweep 
mode, however, they provide synthesizer correction only at 
the beginning and the end of each sweep b^md^there is no 
frequency coiTcction during tlxe actual sweep, The HP 8^^750 
Series [Fig. 1 ) establishes a new standard of swept fre- 
qucncy accuracy by being fully synthesized in aE sweep 
modes, including fast analog sweeps. 

Tlie HP 83750 Series of synthesized sweepers is part of the 
HP 8370 family of microwave sources. This fanuly also in- 
cludes CW generators mid synthesized signal generators, 
which are discussed in the article on [>age 0. Pour HP 8^3750 
sweeper trwdels are cuiTently available: 

HP 83751 A 
HP 8375 IB 
HP 83752A 
HP 837528 

2lo20GHss, +10dBni 

2 to 20 GHz, +17dBm 

0.01 to 20 GHz, +10 dBm 

0.01 to 20 GHz, +16 dBm from 0.01 to 2 GHz, 

+17 dBm from 2 to 20 GHz. 

Extended frequency coverage to 110 GHz is available wiUi 
HP 8;3550 Series millimeter heads, using the optional source 
module interface. Other options mclutie a 70-dB attenuator, 
a high-stabihty time base, and alternate output connector 
type and location. For Held test apphcations, a portable pack- 
age is iilso avaUable, which adds a tilt-bail handle, rubber 
bimipers, rear feet, and a protective front-panel cover. 

Fundamental Oscillator Technology 

The RF l>lock diagram of the HP 83752A sweeper appears in 
Fig. 2. A dual \1G oscillator (DYO) generates a microwave 
signal between 2 and 20 CiHz tising two separate oscillators 
moimted in a common niagnet assembly (see article, page 
46). One oscillator tmies from 2 to 11 GHz, and the other 
tunes from 11 to 20 GHz. 

Fig. 1, The HP 83750 Series syn- 
Litesizocl eiweepers are packaged 
in a fjl-findjird nve-inch-ldglt Lnbi- 
iiet- The\' fit ill tho saine Cdck 
panei space as the older HP B35Q 
Series noiisynthesized sweepers. 

3 S April 1 JI93 Hewleu-PackanJ Joi3 mat 

)Copr. 1949-1998 Hewlett-Packard Co. 


1110 20 

2 1Q 20 GHz 
ID Synthesizer 





VfG Rftei 

Q.m to 20 

ALC and Putse 


S.41 10 7.q 




0.01 ta 2 QHz 

ALC and Pulsfi 

Pig. 2, Rt' block diagram of the HP aS75Q Series swet^pers, J\w RF chain includes four new iiiinroeircuit designs. 

Previous HP sweepei^ used a lower-^frequency oscillator 
multiplied up to the desired output frequency. The advan- 
tage of the fundamental oscillators in the IIP 83750 is that 
th€^y produce no suhharnionjcs. 

The two oscillator outputs feed into a modulator ainpUIier 
(ModAnip) nurroeirruit, which provides signal switching 
and disirihutloni amplification, and ALC and pulse luocliila- 
tion (see art icie, jjage 46). A low-level outt^ut goes to the 
sampler assembly for use by the synthesizer. 

The main 2-to-20-GHz output signal from the ModAmp is 
routed to a switched amplifier filter deteti^ir (HAFD) micro- 
circuit, whicli provides power amplification and tAvo stjiges of 
YIG filtenng (see artkie^ page lij). Tlie filtering reduces out- 
put hanntmics to less ihim ^5 dBc. A significant advantage 
of the 1:7G -filtered output is extremely low bmadban<l noise, 
which is important for scalar network analysis applications. 

T]\e SAFD nucrocircutt also coi^tains a broadbaixd automatic 
level conirol (ALC) detector, whicli is used for power level- 
ing over the entire 0,01-to-20-GHz fiecpiency range. This 
technique avoids the power discontinuity commonly associ- 
ated w ith sweepers that use separate leveling detectors for 
different frequency ranges. 

To generate a signal below 2 Gli2, the YIG oscillator is tuned 
between 5.41 and 7.4 GHz. This signal mixes with the outpul 
of a fixed 5,1-Gnzs>iithesiz*^d oscillator to produce tbe 
O.Ol-to-2-GHz output. An «implifier and filter follow. A nitytjr 
objective of this design was to reduce nonharmonic mixing 
spurious signals to less than -50 dBc for output levels less 
tlian +5 filini, wliili^ minimizing broadband noise. 

Frequency Control 

The microwave oscillator and filter in the HP 83750 each 
contain a finy sphere of cr>stalline yttrium iron garnet 
O^G). HTien subjected to a magnetic field, a YIG sphere 
resonates at a microwave frequency that is directly propor- 
tional to tlie strength of the magnetif* field. The sphere is 
moimted in the pole gap of an electromagnet. The fieki 
st.rengtli, and thus tire YIG resonant rreqnencyn are directly 
proportional to magnet current. 

The job of the YIG driver, Ftg. 3, is to generate a current pro- 
portional to the riesirerl fretjuency, A sawtootii -shaped signal 
produced by the swee^) generator board is scaled and offset 
by the YIG driver to sweep the YIG oscillator and filter over 
the desired frequency range. S mallei' correction signals from 
the sweep generator compet^sate foi- nonlinearities and 
delays in the YIG frequency -versusHiair rent response. 

Even if the phase-iocked loop synthesizer were not present^ 
this arcbitecture would produce a swept microwave signal 
with fair frequency accuracy The need only apply 
a small correction voltage to eliminate any remaining errors. 

The function of the sweep generator botu-d (Fig. 4} is to gen- 
erate tbe main sweep ramp and several f orrcction signals. 
Previous instruments used an integrator to foiin the sweep 
ramp. Such an integrator must be carefully designed to pre- 
vent its drift and nonHnearity fron) contributing to swept 
freqtiency error. In tht^ IIP a3750, a digiid-lo-imLilog converter 
(f)AC ) generates a stepped sweefi ramp sirtuiltaneously witli 
the analtyg ramp. Once per step, the two ramps aie com- 
pared j and the sampled en^or voltage feeds back to conecl 

)Copr. 1949-1998 Hewlett-Packard Co. 

April 1 993 H f w J (' 1 1 - 1 ^K karil Joumai H ft 


Mali Amp 


VIGO river Beard 


ALC Board 





Fig, S. HP 8:^750 fn rinency f nnrrol bltK'k diagrarn. Hiiliki? previous designs, the synthesizer in itu- HP 83750 remains locked thLrougliqiit live 

any integrator errors* Ttie resulting sweep ranip reflects the can be scaled and offset to sweep between any two voltages 
accuracy and stability of the DAC output while retajning 
true ax\alog sweep. 

The analog sweep ranip is available to the user as a 0-to-lOV 
ramp (Sweep Out) whose amplitude is independent of fre- 
quency span. An<jlher outpul voltage (V/GHz) proportional to 
absolute frequency Is also availalile. At the users option, it 

between -10 and +10 volts. 

The Digital Signa! Processor 

The digital sweep rainp and four coiTertion voltages are gen- 
erated by five DACs. A TMS 320CiO cilgital signal processor 
(DSP) calculates appropriate values in real time and loads 

J .. 

Sample ard 




{To VIG Driver) 







Swevp Otn 
\ Fro nt/Roar Pa ne Is) 


IRear Panel) 


Fig- 4> The sweep iterator assembly produces aii analog mmp and four correction signals for use by other ass«^niblJes, 

40 April 1993 Hewlett-Packard Journal 

)Copr. 1949-1998 Hewlett-Packard Co. 

them into the DACs as the instniinent sweeps. When the 
instniment is turned on, the host microprocessor (an 
MCSSOOO) downloads calibration data to the DSP. After 
tJiat. the host need only update the DSP with new start and 
stop frequencies, power, and sw€^p time whenever the user 
changes those %'alues. The DSP automatically calculates the 
correction voltages based on thai data. 

The DACs are updated between 101 and 1601 times per 
sweep, depending on sw^eep time. A circuit on the timer 
board generates) 101 to 1601 nigger pulses per sweep that 
are applied to the DSP interrupt input. The interrupt causes 
the DSP to update all fiv^e DAC outputs simultaneously. 

The DSP has a minimum of about 100 microseconds be- 
tween pulses to calculate upcoming DAC values. In this 
time, it must compute three thirdorder interpolations, one 
straight-line inten>oiation, two sweep tcimps, and two com- 
plex delay comt^ensalion w^aveforms, A specid third-order 
curve-fit algoritiim is the key to achle\ing this performance 
using inexpensive DSP hardware (see below). 

Two of the third-order inteq>olations are used to calculate 
linearity correclions for the DYO and SAFD. Actually, the 
synthesizer alone could correct for YIG oscillator nonlinear- 
hy, bul Uiere is no guarantee tliat tlie oscillator and filter are 

identical in tliis resi>ect. The DSP correction ensure that the 
oscillator and filter track each other throughout the sweep. 

Even more criticaj, for both tracking and sw^ept frequency 
acciuacy, is delay compensation. ItVTtenever the current 
through a \TG magnet is changing, the HG resonant fre- 
quency^ la^ the current. The iin^e lag is a function of sweep 
speed, start frequency, and previous history of magnet cur- 
rent. This delay causes fast transienis to occur ai the start of 
each band that are difScuit for the svTitiiesizer circuitry to 
correct for. The DSP uses a proprietary algorithm to calrti- 
late delay compensation, w^hich is added to lineEuity correc- 
tion and output to the appropriate DAC, Using the DSP to 
perform this fimction replaced a boardful of sensitive analog 
circuitr^^. It also made it easy to try^ many different com- 
pensation w^avefoniis in our iiuest to achieve a new standard 
of sw-ept frequency accuracy. 

The third use of the third-order interpolation algorithm is for 
the powder clamp output The ALC board uses tiiis signal to 
limit maximum RF drive level to the SAFD. CKerdrinng the 
^10 filter can cause sciuegging (low-frequency amphtude 
oscillations), w^hich low^ers the available output power 

The ALC output controls the instnmient RF powder level The 
ALC board compares this signal to a logged version of the 

Third-Order Curve-Fit Algorithm 

The frequency-versus-currenl transfer function of a Y[Q o&cillatDr ar filter rs orrly 
appfoxfTTiately linear. Product ion testing measures the deviation from Imearity at a 
series af calibration frequencies and stQj'e3 this information in the instrument's 
nonvolatile memory 

In Fig. 1 , the Ys indicate the required correctfQn at each calibration point The Xs 
indicate the nominal frequency at each point. To interpolate between calibration 
points, we use a iliird-order curve y(x). defined by four parameters A. B, C, and D. 
A different set of parameters must he calculated for the intervaf between each 

pair of caiibration points. 


= a(x 

" X. f + B(x - 

- Xfc)' + c(« - 


+ D 


— ^^_ 

- ^^ 





\ — 




I (Alt) 

B^ A - C - + Vj 
(Ax normaNzed to unity } 

Ffl. T* This ttiird-orcfer algoriThm produces an mtemolaied curve that passes e;iactlv through 
each calibfBtton paint and has a rannnuous fiisi denvative Onfy add and sJiift opeFHiiQos.are 
rsquifed to compute the coeHtt:i0nts A, S, C, and D. 

The most straightforward way to calculate the four parameters is to generate four 
equations by setting ylx) equal to the four closest calibration points, and then 
SQive for the four unknowns A, B. C. and D. Besides being computationaliy inten- 
sive, this method results m sharp edges at calibration points, that is, it has a 
noncontinuous fir^t derivative. 

A well-known method called the cubic spline uses aJI H available calibfation 
points (0 generate a curve with continuous Mth-order derivanves. Unfortunately, 
the calcuJatJDns would take much longer than the available 100 fis Other inter- 
po I at ion algorithms, such as the B sphne, are faster, but the resulting curve does 
not pass exactly through the calibration points, 

The method employed in the HP B3750 Series sweepers uses four equations to 
solve for the four unknowns. Two equatJons result from constraining the curve to 
passexacdy through the two nearest calibration points. Y, and Y,*] The other two 
equations result from setting the slope of the curve at the segment endpomts equal 
to the slope of a lino connecting the two points that bracket each endpornt. This 
guarantees that the slope of each segment wilf match the stope of the adjacent 
segment where the segments connect, so there wdl be no sharp edges 

Solving these four equations results in the equations for A, B, C, and D shown in 
Fig. 1 . Mote that all multiplications and divisjons are by factors of two This iriakes 
the computation very efficient since multiplying or dividing by 2 is equivalent to 
shifting the binary number left or right one bit. Shifting can Dccur autDmatic^lly as 

the DSP loads the number into its accumulator. 

Calculating A. B, C, and D requires 33 DSP cycles or 6.B ^is, The total time to do all 
computations required for the three separate interpolated outputs is 1 53 cycles or 
3a6 US. 

Alan Bfoom 

Development Engirteer 
Microwave Instruruents Divisiort 

April lfS3 KewNil-Pm-kHTd 41 

)Copr. 1949-1998 Hewlett-Packard Co. 

Sample and SiarT-of- Sweep 
Ho^d Correcliofi 

S qt 


Phase . 

Detector . I^f. 


Prctune and Swee|i 


Fig. 5. Traditional synLheslzer 
block diagram, in Hip r. radii ional 
"lock aiirl ruJJ ' s>7i!!jesizen the \1G 
osdilator is phiasf? lucrkfid at Th(^ 
Ht4irt of the sweep lo a multiple of 
a low-noise, stepped CW siiitlie- 
sizer frequency. Tlie analog cor- 
rection voltage fram tlie phase 
detector is sampled and held fur 
I lie duration of the sweep. 

detected RFcmtpiit level ajid atljusus nuKlulalor current to 
make the two signals eqtial. Detector calibration and tem- 
perature compensation are haiidled by additional ciniutry 
on the ALC" bo^ml. Tlie DSF ALC signal includes basic RF 
power level, flatness compensation, and power sweep. 

"Flatitcss compensation" refers to tl\e use of factory calibra- 
tion anays to coirect for the frequency response of the cou- 
pler detector located in tlie SAFD. In addition, the user can 
enter arrays of tip to 801 points to correct for fltc* response of 
the hsit's test system. These user calibration points can be at 
any Frequencies wilhin the instnuncnt^s range. Since the third- 
order iilgorithn^ requires equally spaced calibration points. 
ALC flatness c^oinpensation nnist use linear interpolation. 


Hewlett-Packard microwave synthesizers (for example the 
HP S^^&) Series ) have traditionally itsed the block diagram 
shown iji Pig. 5. The local oscillatoi' (LO) drive for the sam- 
pler is a iow-noise stepped synthesizer Its outjntt h^is coarse 
frequency resoiutiont but extretnely low phase noise. It is 
not able to sweep its output frequency. The IF output of the 
sampler is then locked to a Mgh-resolution syntliesizer, often 
a fractional-N loop, which pro\ides the output frequency 

The only loop in the traditional block diagram with swept 
capability is tlie fractional-N loop. II is used as the reference 
for the saJTipIer IF phase-locked loop. Therefore, its output is 
directly translated (mixed ) lo the RF output. Tiiis limits the 
width {>f a synthesized sweep to the width of a fraction;i]-N 
sweep, whicii is tyi:)ically tens of megaliert^- For broader 
sweeps, tlie traditional syntlieslzer musi sweep tuilocked. T\\e 
start frequency is phase locked, then t!ie phase-locked loop 
error voltage is santpled and held while tlie fre<|uency sweeps 
open-loop. This technique Ls called "lock and j ull." Ijater 
instruments use the synthesizer to count the stop frequency 

mvd at>piy a coiTection to subsequent sweeps. Tliis makes 
botli the start and stop frequencies quite accurate, but tlie 
actual sweep is still performed open-loop with significant 
frequency errors l>etween the endpoints. 

In the HP 83750 (Fig. 6), the fractional-N loop is used as the 
LO for the sam filer. The fraciional-N loop output lret|uency 
LS multiplied by the liannonic nmnber aitd 1-raxLslated to tlie 
RF output. This gives tlw HP 83750 tiie ability to perform 
tnie s\Titliesized broadband iuialog sweeps. If the fraction- 
al-N loop sweeps an octave, the RF output wdtl sweep an 
octave. For example, the IIP 83750 can sweep the full ll-to- 
2t)-Gnz RF band in one continuous phase-locked sweep. 
This improves the swept frequency accuracy of the instru- 
ment by at least an order of magidtufie (Fig. 7). Swept fre- 
quency errors mv now limited lo tinung uncertainties and 
transients that cannot be completely removes! because of 
limited phase-locked loop bandwidth. Botli of tjiese errors 
improve linearly with reduce:! sweep s(>eed and span. This 
arclutectiire gives the HP 83750 Series state-of-the-art swept 
frequency accuracy, aUovring very precise, higli-gpeed swept 

The HP 83750 fractionaLN assembly contains a voltage- 
controlled oscillator (YCO), a fractional dividen and a 
phtise-locked loop. This circuitry can synthesize a 250^to- 
500-MHz si^nnl with resohition better than 10 nllz and excel- 
lent swept freqiiency acciuacy and phase noise (see page 
44). The fractional-N phase-locked loop output Is the LO 
drive for the microwave sampler, A coupler sends a portion 
of the YIG oscillator output signal to the RFport of the sam- 
pler. The action of the sampler in the frequency domaui is 
sunilai' to that of a hannonic mixer The IF output frequency 
ffP of the sampler is a function of the LO and RF frequencies 
fixi and fpF and the harmonic number N: 

ftp = ffiF - Nf|j t. 




Error Correclian 
During Svyeep 


to op 




Pretune and Sweep 


Fig* 6. HP mim synthesiser 

block diagram. h\ the HP 83ToO 
synthesizer, tlie ^Ki osi illator Ib 
phase locked to a multiple of a 
fractional-N sjTithesizer fre- 
quency during ttie sweep. 

42 /Vpril I9\r3 He wUn -Packard .lourrml 

)Copr. 1949-1998 Hewlett-Packard Co. 


^ ■ 


-f — 1= 

-h-i — t-H 


6 1 2 3 4 S G 7 S 9 10 II 12 13 14 t§ tfi 17 IS f9 20 
Frequency (GHz} 


I 0.1 f 




i- -0,1 





H — I — I — \ — I — h 

1 i I 1 


1 2 3 4 S 6 7 fl 9 10 11 12 13 14 IS 16 17 18 19 20 
Frequency (GHz J 

Fig. 7* (a) HP S.3750 swf^pl frequeucy accuracy with n UJO-nia 
sweep, (b) Impn^vernent obtaiiied at a slower .sweep speed, iii UiiB 
case a sweep time* of I h. 

The YO loop assembly is anotJier phase-iockod loop. Tt aiiipii- 
fies and limits the IF output of I he sanipJer, cli%d£les it by 10, 
anfl Iheii ronects Uit^ \1G osl illalor Irequeiify to phase lork 
the IF/ 10 signal to a 1-MHz reference. This i oustraiiis the IF 
output of tJie sampler to be 10 MHz. The output frequency of 
the YIG oscillator (fjiy) is then: 

fRF ^ NfLo + 10 MHz. 

The harmonic ninnber N ranges from 7 to 4L This yields a 
range of 2 to 20 GHz for the synthesi:«e<i YTG oscillator output 

This synthesis structure places stringent perfonuance re- 
quirements on the fractional-N assembly. The fretioency 
accuracy, resolution^ and phase noise of the Praclional-N 
loop are fill multiplied by the harmonie numben Analog tech- 
niques improve the swept frequency accuracy of t lie phase- 
locked loop enough lo achieve our performance goals. Ex- 
cellenl frequency resolutior> is easily altauied Uy usnig48-bil 
accumulators in the frat tional ilivider. Tlie phase noise, 
however, is an inherent limitation of the IIP 837.^3(1 iirchitec- 
ture becanse fraetional-fJ synth^'si/ris have higher noise 
than stepped syntJiesizers. Thi^ causes more close-in phase 
noise than that exhibited by traditional HP synthpsizers. The 

fraeclonal-N phase-locked loop band%vidlh and filtering are 
optiniized for CW phase noise. The resulting performance is 
better than the nons>"nthesized HP 8350/83592 at aknost all 
offsets, and the residual FM is considerably improved. This 
performance should easily meet the requirements of most 
sweeper applications, 

Tlie HP 83750 synthesizer was designed for excellent swept 
frequency accuracy at low cost. A fixed frequency refer- 
ence replaces the high-performance stepped synthesizer 
used in the traditional block diagram- The digitally corrected 
fractlonal-N svTithesizer is much less expensive than the 
fraetional-N synthesizers used in previous microwave instru- 
ments. Tins new architectuie provides synthesized frequency 
accuracy at id broadband phase-locked sweeps at a price 
usually associated with open-loop sweepers. 

Self Test 

The HP 8-3750 includes an analog bus for self-test and cali- 
bration. The analog bus is a single wire tJiat connects to 
most printed circuit assemblies. Each assembly includes an 
analog switch that can connect the bus to atiy of several test 
points. By properly setting these switches, firmware self-test 
routines can measure voltages throughout tlie iiLstnmient 
usuig a single 12-bit aiialog-to^:ligital converter (ADC') located 
on the CPU board. 

Over 150 tests can be executed with a single key press. 
When a tiardware problem occurs, it can have far-reaching 
effects, causing a liandful of test routines to report failures. 
For example, an ituorrect power supply voltage might cause 
aO circuits tliat use that voltage to "fail." Finding the most 
independent failure and reponing tliat to the operator is the 
goal of the diagnostic feature. 

F(jr each test in the instrunient, a Ust of its dependencies 
was i'reated. For example^ the list below suggests that the 
test of the Sw&ep Out signal requires tliat the digital sweep 
DAC, timer #2, the timer intemipt, the DAC trigger, and the 
sweep trigger tests all work properly. If any of these tests 
has failed, then it is inappropriate to suspect the Sweep Out 
cLTcuits as the primaiy cause of failure. 

Test Dependencies 


After building a comprehensive table of dependencies we 
used a computerized algorithm to sort all tests into a single 
ILst sorted in order of interdependence. IiLsmuuent Onnware 
uses tills list to re|>ort the primary faihire— the one the 
service technician should investigate. 

Test limits can be changed in the field to accommodate 
tuudware upgrades. A test jjatch feature, similar to the one 
used in the HP 8360 Series, allows tlie customer service or- 
gtuu nation lo alter test limits mtd store them into nonvolatile 
memory. (Tlu^ original <iefauli limits are still safely retained 
as well J Self-test algoritlmis look for test patch limits fusi 
bi*foi t* usijig tlu* tlefault limits. Both default and test patch 
liniiLs, as well as jueasured test data^ can be read via the 
HP-IB eonnec tor (IEEE 488, fEC 625) on the rear paneL 

Ar>nl UW;l HewlMit hirkitrcf Jriiimal 43 

)Copr. 1949-1998 Hewlett-Packard Co. 

A Digitally Corrected Fractional-N Synthesizer 

Fiacttorjal divider,-! are used to achieve arbitrarily fine frequency resolutian in a 
phase-! DC ked loop synttiesjzer. NDrmally, frequertcy dividers can only produce 
integer divide ratios. Fractional division is accompfished by alterr>atiny the instan- 
laneous divide number between N and N+1 . Accumufators controj ttie number of 
cycles each divide nurnher is used. The fractional divide number is the time aver- 
age of the instantaneous divide number. It a fractional divider is used in a phase- 
toe ked loop, the output frequency (1^^^! is: 

Where M,F is the fractional divide number and fref is the phase- locked loop 
reference frequency 

The phase-locked loop is in fact attempting to hop the VCO frequency between 
Nf^ef and (N+1 [fief ■ This causes cons ids rabie phase modulation on the VCO. Most 
HP fractipnal'IM synthesisers ifig. 1 \ have used a technique caHed anaiog phase 
interpplatian (API) to remove this phase modulation.'' API uses the accumulators 
that control the instantaneous divide number to predict the phase error resulting 
frDm the fractional division, A DAC sums a canceling signal into the output of the 
phase detector. This analog correction must be incredibly precise to achieve the 
necessary spurious performance. 

The HP 83750 fractional-N synthesizer (Fig/2) uses a dtgrtaHy-corrected fractional 
divider deuelaped at HP's Spokane Division.^ The divider uses the same concept 
as sigma-delta analng-to-digital converters (ADCs), These converters operate hy 
greatly oversampling the analog input with a coarse (often one-bit) ADC. This output 
is then digitally filtered to eliminate out-of-band quantization noise. Sigma-delta 
modulator techniques^ can then be applied to shape the quantization noise so that 
most of the noise js pushed outside the frequency band of mterest The quantization 
noise is removed by filtering. 

in the fractional divider, the fractional divide number is analogous to the analog 
input to the interpolative ADC. The integer divider is analogous to the one-bd ADC, 

(125 kHr} 

Loop Amplifier 
and Filter 

r u 




*Divide Number = 


Rg. T, The tfiaditiorsaf fractionaM^ synthesizer uses an analog phase inte^polatof jAPI) to 
eliminaTE unwanted phase mcdiilaiion of the VCO The API needs 0,03% accuracy to reduce 
spuriniis sidebands to -70 dSc. 




LfK»p Aniplrfter 
and Filter 






N+3 - 
H+2 - 

'Oivide Number = ^ 

N-1 - 
|« 2 - 

H-2 - 

Fig. 2. The HP 8375QfractfCinai-N livnthesi^er uses digital correctian to shape the quantization 
norsE. The phastf- lucked fuDp fiUera and rerno\'es ihe noise. 

Digital techniques shape the fractional -division noise and push it well outsidf the 
bandw»dth of the phase- Incked loop. The phase-lonkeri loop acts as a low-pass 
filter and removes the fractional division noise before it is applied to the VCO, 

Tlie digital correction changes the integer divide number every reference cycle, or 
every 500 ns in the HP 63750. The divide number is not toggled between N and 
M4I, but can take on any integer value between N-3 and N+4. The digital correc- 
tion causes the divide number to vary in a random fashion, protliicing pure noise 
with no spurious content. This noise is shaped so That it increases at a rate of 40 
dB per decade of offset frequency The phase-locked loop low-pass filters this 
no^se so that it never nses above the phase noise of the VCO. In this manner, the 
phase errors produced by fractional division are removed without the cost size, 
and complexity of the API circuitrv traditianaJly used m fractional-N synthesis, 


Ihe research and development of the fractional-N and prescalor ICa was done 
by Brian Millef and Bob Conley of HP's Spokane Divisior> Tfiey also provided 
corisultation and support to the many users of these parts within HP. 


1 . D.D, Datiielson and S.E. Frosatfi, "A Synthasized Signal Source v^Jth Function Genarator 
Capabilities." Hewtett-Packard JmmlM 30. no 1. January 1379, pp. 18-26. 

2. B- Miller and B Conley "A Vlultiple Modulator Frsdional Divider,'' Proceedings of The 44th 
AnnuBi Sympasim qr ffBQUsncy Control 199€, pp. 559-56S. 

Jason Chodora 
Development Er^grneer 
Microwave Instruinents Of vision 

A significant new feature of Ihe HP 83750 is that instrument 
finnwaie Ls stored in flash EIPHOM, a t>i)e of reprogiamma- 
ble nonvolatile memory. This allows instrument firmware to 
be upgraded in t he field to add new features or to fix bugs. 
Rmiwai'c upgrades are distributed on 3.5-inc'li disks, which 
call be read using an HP 9122D HP-IB disc drive. A smaller 
nonreprogrammable boot ROM contains the fuTiiware load- 
ing routine and some basic seif-test routines that execute 
whenever the histmnient is tinned on. 


The HP 8-:3ToO uses large arrays of caiibratton cottstants to 
correct for YJQ filter linearity, YTG oscillator hnearity, and 
power fi atness. Tlie uistrument can generate these arrays 
automatically. The only other eQUtpment requked is a power 
meier for power cahbration. 

A front-panel Peak button causes the instnmient to align 
tlie YIG filter automatically at each of approximately 230 

44 Apnl 1993 Hewfe tt-Packar<l Journal 

)Copr. 1949-1998 Hewlett-Packard Co. 

frequencies between 2 and 20 GHz- At each frequency, the 

analog bus is used to monitor ALC^ modulator drive voltage 
as the YIG filter frequency is varied. V¥hen a peak is found, 
the proper corre<.^tion value is stored in memoiy. This func- 
tion is also called autotrai'king. 

YIG oscillator calibration is a^'aijable \ia a Special Function 
menu. In this case, the analog bus monitors the YO loop 
correction voltage and adjusts the calibration constants 

liniil the voltage is zero. 

A fi^nt-panel Flatness Cal button allows automatic power 
level calibration using an IIP 437B, 4;]8A, or 70100A power 
meter The user can ol)tain calibrated power at any point in 
a test system by caiihrating with the power meter located at 
that point. 

Placing tin\e-consim\ing calibration routines in firmware 
lowers irLstrument cost by reducing test rime. For exainple, 
aulotraeking via art external controller running a BASIC 
program took 50 minutes. The firmware autotracking rou- 
tine runs in less tiian one minute. Faster calibration also 
gives better accuracy, because there is less frequency drift 
betw^een the beginning and llie end of the procedure. 

Product Design 

Ruggedness, light weight and serviceability were the goals 
of the HP 83750 prodiirt design. Extensive shock and vibra- 
tion testing was done tCJ ensure thai the iristrument meets or 
exceeds HP standards for niggedness. An optional portable 
package witli tilt-bail handle is available that meels the 
requirements of MIL-T-28S0OE T^pe III Class 5 Style D. 

The weight was reduced through the application of modem 
technology. A switching power sapply eliminates the heavy 
power transformers found in earlier designs. The dii;d YIG 
oscillator combines two separate nticrowave oscillators 
within one magnet stmctme. Other sweeijers that use fimda- 
menial oscillators require two or three devit-es to cover tlie 
same frequency nmgc, w^hich adds to cof^l, \v<"i,L^lH ;iiid 
power consumption. An HP 8<3752A sweeper vviiglis 16 kg 
(36 lb) compared with 22,5 kg (49.6 lb) for an HP 8:350B witii 
HP 83592A plug-in. 

Servicing an HP 83750 is facilitated by ease of access (see 
Fig. 8), A central cardcage houses most of t he printed circuit 
boards. Test points are located at the tt>p <;)r each board. A 
board can also be raised on m\ optional px lender t>oard for 
more extensive troubleshooting. Tlie power su|>i)iyt bolted 
to t he lef^ side of tlie chassis, is replaceable as a unit. All 
microcircuits are located on an RF deck at the right side of 

Fig. 8. hilemal view of tht* HP S^TT^O vtmssls. 

the chtissis and can be accessed by removing the top and 
side instnmieni covere. The entire RF deck can be ren\oved 
from the instrument without disnipting any RF connections. 

Ac know ledgme n t s 

The authors would Uke to thank the many other engineers 
who made valuable technical contributions to this product. 
Stewart C^haimson designed the ^IG driver and RF interface 
electronics, and developed tlie algorithms and data struc- 
tures for "^TG oscillator and filter delay compensation and 
linearity. Lance Haag fleveloped calibration and iilignment 
procedm"es, evaluated RF system perfomiancet and devel- 
oped the sampler assembly. Steve Punte was tJie technk/al 
leader and Doug Bender provided management support for 
firmware developnieiit, Other meml>crs of the finnw^aj-e 
team incliided .lirii (Jrisluiw [hardware and HP 87G7 control), 
Thanh Hey man i iiser interface), Mike Seibel (SC PI couphng 
and flatness (niNI i jr i. m), Sue Wood (self-test), and Phuoc 
Tian ;uid Dan Podt-Jl { lli'mware QA). Roger Valentine and 
Andy Smith did the t>rodiicl (iesign. Jon Jasper was responsi* 
ble for new pnuliict introdiicfion product ior^ engineering 
and test deveiopment. Jon Kiser coordinated t be envirtjn- 
mental testing. We would also like to thank Arien Detblefsen 
and Rolf Dalichow for tlieir support.. 


L R. Ualichctw and D.E. lAiltuier. "'A Brcjadbaiid^ I^^illy Prograininablt* 
Microwave SwtH^p iysvilistoT,'" Hewh'tf -Parkyird Journal. Vol 3:^ no. 
2. Fotintary 11182. jip, 3^10. 

2. H.E DijlatL J.R RvgrnLrA, and J.E. Bossaller, "A Funnily of High- 
Perfomiaiice Synthf^sj:5(?d Kwoei>f'r'rs,*' Hmvielt-Patkani -hmnuil Vol 
42, no. 2, April 1991, pp. fi-16. 

)Copr. 1949-1998 Hewlett-Packard Co. 

April mm He wlett-BK'kariJ Jo i m lal 45 

Microcircuits for the HP 83750 Series 

Four custom microcircuits provide the basic output signal, the RF band, 
signal switching and distribution, amplification, ALC and pulse 
modulation, power amplification, and two stages of YiG filtering. 

by Eric V.V. Hey man , Rick R. James, and Roger R, Graeber 

Tills aHiflp (iisc'uases thp design of tht^ four custoni mjtro- 

circtiils designed for the MI' 8^^5750 Series sweep oscUlators. 

Tiie niicrocirnuits are: 

The dual ^'IG oscillator f DYO) 

71ie switched yinplirier filler detector ( SAFl)) 

The O.Ol'to-2-GHK helerodyiie i^and microcircuh (lletBajul) 

The combiner nKMtulafor ajitpuner (MndAmp). 

Dual YIG Oscillator 

The signal for the IIP 83750 Series sweepers is general ed in 
ttie fhial VI G oscillator microcircuit Tlie DYO is actually 
two VI G oscillators in one magnetic housing. One oscillator 
covei^ ti\e S(>an from 2 to I ! GHz ajid the other' covers from 
1 1 to 20 (tHz. Tlie output power exceeds 20 niW from sepa- 
rate outiiuts for each band. 

Tl\e high-band 1 l-t<>20-GHz oscillator consists of a VKi reso- 
nator and a single GaAs IC chip tJiat contains both the oscilla- 
tor and buffer stages. Fig. I is the schematic diagram. The IG 
is faliricated nsing an HEMT GaAs IC process with an fj of 
50 CtIIz ajid an f^,,^^ of 100 GHz. The chip (Fig. 2) measures 
only 960 by 960 ^m. 

Tlie oscillator stage consists of a 200-[mi FET in a source 
follower configuration. Tlie feedback is generated by a 
0.2-pF thin-iihu caparitnr connected tietween the source 
and grovuul. This IVedtvick geru^rates an imijedance lookirig 
into ttie gate of [he lievice that Inis a negative real pai'l ai\d 
thus has a reflection coefficient greater tiian !, which is a 
necessary condition for oscillation to begin. ' The condition 
for oscillation to begin is: 


!\ice* resttnator 

> 1, 

where ^^^.^^i^.^. and Tj-, 

' are the reflection coefllcients 

of the device and resonator, respectively. The condition at 
oscillation is: 

1 tli'viff ' resonator ~ ^- 

Fig, 2. l*lioTu^[Ti|:jh or rho i )\i i chip. 

This relationshif* is achieved as Ftj^nrK-e is reduced by limiting 
during the buildup of oscillation. Tlie phase condition is satis- 
lied by a shift along the resonator cuj'\a\ possibly allowing 
the oscillation to occur somewhat off resonance. 

The source follower configuration has the potential to oscil- 
late at undesired fretinencies above or beIo\\^ the desired 
band. Tliese nndesired oscillation conditions, called lockup 
modes, arc* a result of the interaction of the \1G conphng 
loop para.sitics and tlie active device. The oscillator circuit 
must be designed so that there is insufficient reflection gain 
to support the lockup mode. At the low end i>f the l>and tins 
Is accomplished by placing an inductor in parallel with tlie 

I ^dc Integmtetf Circuit 



Fig, 1. nVO high'band sch<!imatic 

46 April 19(*3Hc^wlt^ii-Paf kardJotmrnt 

)Copr. 1949-1998 Hewlett-Packard Co. 

Fig. 3. Photograph of the DY(J. 

source feedback capacitor This has the effect of rediicing 
the capacitance on the source and Ihns the reficflh>n ^airi aJ 
lower frequencies. In afltiifjon. a high-unpedaiice ccmplijig 
loop is used tiiat does not pro\'ide the pro[*er ])hasp relation - 
siiip for the lrK7kup mode. To avoid iockiiii at fJie lijgh end of 
the baiid the transmission line betw^een the device and the 
resonator is kept short- 

The buffer ainplifiei" stages consist of a 300-^m FET fcjl lowed 
by a 400-um FET. both in the common source configuration. 
Tlic oscillator stago is matched to the buffer amplifier using 
a short length of transmission line. The primary' purpose of 
the buffer stages is to provide isolation and therefore a 
si able match to tbt^ oscillator stage, making the (JsciUator 
frequency independent of the load. 

The YIG (yttrium iron garnet) resonator provides the high-Q 
tuning ciicuit for the oscillat or Tlie high-band resonator is 
constructed of a 300-^m-diamcter, untio]jed YIG sphere c*en- 
lered in a multituni coupling wire. TJie rati<j of sphere to 
lonp dianieters is a trade-off betwc^en suppression of spuri- 
(His resonmices and oscillation strength. The \1G resonator 
provides a rt^sonance that tunes linearly with an applied 
magnetic field.^ 

Tlie ll-to-20-GHz higlhh^iiid oscillator Ls budt on a O.OllMiuh 
molybdenum ciirrier (Fig. 3 ). This canler is held to the lid by 
studs inserted in the lid. The cairiers function is fo prtjvide 
a continuous ground plane. The YIG (xaAs IC is soldered to a 
small heat spreader and then epoxy -attached to the carrier 
A 0.010-inch fused silica microstrip circuit is epoxy -attached 
IjcLween the YIG resonator and I he JC to provide the proper 
transmissiDn line length. The output circuit is a O.OiO-incli 
sapphire micros trip cinuit wliic:h prcjvides out^jut matching 
and transition to a right-angle SMA connector. 

The low-band 2-tihU'Q}]z tjscillator consists of a YiG res<jna- 
tor, a bipolar transistor osciliati>r stage, a tnatcliing network, 
and a hroadluuiil hiifler amtilifier (Fig. 4). The nst illator 
^stage uses a silicon bipolar transistor widi an fm.,^ of 22 (J Ik. 


Tra re ling- Wave 


Fig. 4. DYO low -band schematic diagram. 

The transistor is configured as a common base circuit with 
an iufJuctor in series i^ith the base terminal. The inductor is 
rcidized as a length of transmission line. This inductor trans- 
fomas to A negarive real impedance at the emitter port and 
thus jueets ihe above criteria for oscillation. The collector 
port is tenninared in a matching network that prtnides load 
conditions to optimize ostillation strength, harmonics, and 
lineiuity. The bufter stage consists of a S-to-^O-GHz travelir^g- 
wave GaAs IC ampUfier The YIG resonator consists of a 
t>00-jim-diameter 550-gauss YIG sphere in a haJf loop of 
950-um-diamcter wire. 

The 2-to-l l-GHz low-band oscillator is built on the same 
carrier as the higii-band circuit. It uses two fl.t)10-inch sap- 
phire microstrip circuits. Tire first circuit contains the hi- 
pol^u" transistor, the \1G coupling k)c>p, and the c oiicc'tor 
matching circuit. Both the transistor iuid the loop are epoxy- 
attached to the circuit* which is als<.i *^poxy-attached to the 
carrier The traveling- wave GaM IC huffer amplifier is sol- 
dered to a heat spreader arid epoxy-att ached t.o the c;n-rier. 
An rjutput circuit provides low-pass filtering and tiansirion 
to a right-angle SMA connector 

The YIG resonaiors require a dc magnetic field to lune the 
frequency. This magnetic field is applied perpendicularly to 
the apptied RF field. Tlie rcsonmit hequency is relati^d iu the 
€\c magnetic field by the equation: 

fo-Y(Hn + H,) 

where U^y is the applied c\v magnetic tleld, Ila is thc^ intc^mal 
magnetic* field and y is I lie charge-to- mass ratio ( jf an vk^c- 
tron. The magnetic fieid is created by wimting ]iW> turns 
Eironnd a (i-nim-diamet(vr pole tip its sliowti in Fi^. 5. The 
L7-mm air gap nmlvr the pole lip is optimized to maximize 
tuning sensitivity and field nnifonnityH which jiffetts !he rejec- 
tion of spurious resonances. The magnetic- material used is a 
50-50 nickel Iron alloy tliat results in im effective magnetic 
siiturat.ion of fjver -^f) (iHz, The windings are wound in such 
a way as to optimize the internal forces when self-heating 
occurs. These forces can change rhe pole gap and therefore 
affect the tuning sensitivity. FM is accompli shetJ by usuig a 
small 17-tuni coil mounted on the pole tip, which adds to or 
subtracts from the main field. 

Switched Amplifier Filter Detector 

An integrated t nil put niK rtHircuit developed fcjr the IIP 8:i750 
Series synihesizers [>rovidesa leveled < nit put from 10 MHz 
to 20 CJOz with except ioiLiUy low luuimmif s and broadband 
noise. The goal was In trreaie a low-cosi circuit containing 
t he required filtering, amp It ft cat ion, switching, and leveling 
in one pack^ige. Through integration, savings are realizerl in 
packaging, printed circuit lnj^Litls. assembly, and testing. 

Apri] I mi] Me'H It'll par kjirri JDiimii] 47 

)Copr. 1949-1998 Hewlett-Packard Co. 




Fi>f. 5. nijltiwnv dravtiufi rjf theDYO and SAFD magnet. 

This niicrocircuit, called the switched amplifier filter detec- 
tor, t>r SAP"!), has Iwo input paths ati shtn-vni in the l)l()cd< dia- 
grant, Fig, 5, The low-frequcmcy path p^isses 1()-Mllz-Ii>-2.(1~ 
GHa signals through a thin-filn^ low-pas^ filter. T!ii.s filter is 
priniaiily desigt^^d H) n^jeti loc^il osrillauir feedihrongh sig- 
nal.s in the r>.4'to-7.4-(iHz range. It also lieli>s rtHluce hamioriie 
signals above 3 GHz. 

The high-fre(iuenry path eovers 2 to 20 GHz. This jjalh Is 
designed to prr>diKe hetier Ituui -4o-dB(^ hannoiiles at aji 
output power of +10 dHni. The filtering is provided by a pair 
of maguetif ally tuned \1G resonators. Since YIG filters are 
both lossy and exhiliit power hniitiug characteristics, each 
one is carefully tuned to provide sufficient powder and band- 
width. Of particular concern in tliis path is shiciding iunorig 
the various components, Tb attain low harmonics, it is es- 
sential to isolate each sec tton, anrl in [vatlicular ro isolate 
the YIG fiUers from each other. Witli this design, the perfor- 
mance is limited by the harmonics generated in tlie amplifier 
betw^een the two resonators (without tliis buffer amplifier. 

the filters cannot be tnned independently). The amplifier is a 
broadband GaAs MMIC traveling-wave ampUfier covering 
the 2-ro-20-Gllz range. 

fhe magnetic field for the YIG filters is provided by two 
coils- A HHO-f um coil wfumtl on a vei7 high-ijenueabiliiy 
core pro\ides the main 7000 -gauss field within a 1,7-mm air 
gap to tune the YTG filters up to 20 GHz. The coil is specially 
designed to minimize any change in the gap size resulting 
from internal or external remperature variations, wiuch 
would chaugt^ the field inlensiiy and thus the center frc- 
qnericy of I he filter. It is critical thai both filters are tuned to 
file same re.sonant frequency to minimize filler loss. There- 
fore, a small offset coil Is placed close to the uiput filler to 
correct for slight differences in fiekl strength which increase 
witJi frequency. A linear' tnioem-veniusTrcquency ramp is 
sent through this coil to comjjensate for ilie difference. Be- 
cause the YTG fdters must tune with the 2'to-20-GHz YTG 
oscillaion tlie packaging and magnetic design are similar to 
the oscillators t.o reduce tracking errors. 

A pair of p-i-n diodes has a dual function. Switching between 
the low-frequency and high-fretiu en cy paths is just a matter 
of tunuiig botli diodes on or f*lf fhe stM'ond fiuiction involves 
the bridge detector on the fjutpuf The bridge is a GaAs inte- 
grated circuit with tbin-filui resisinrs. Because of their small 
geoixietryi these resistors must he protected from dissipating 
excessive power. If an excessive level is detected by the 
bridge, clamping circiiiti-y on the bias board shuts off the 
t)-i-n diode liias. Under normal oi>eration, this clam]> is only 
a safety featiux^ he<ause th*^ ALC looiJ in the iustnmient also 
Dmits the input power to tlie Hj\FD. F'oU owing tlie p-i-n 
switch, a thin-fiim 20-GHz low-pass filter reduces out-of-baitd 

The last circuit in the HAFD crintains the leveling hricige. 
Because of proper ratioing of resistors, the voltage across 
the bridge dirxle is proportit>ual truly to the voltage incident 
on ttie load mid is inrlependent of ihe signal reflected from 
the external load. Therefore, the bridge exhibits directi\1ty. 
Because the diode is operating at low^ powder levels, its dc 
output vottage Ls propoilional to tlie squaie of the voltage 


0.01 ID 20 

Offset Coil 


ZO to S) 

YIG Filters 


0.01 Id 20 



Main Coit 

Pig. 6. SAFD micrnciieuit block 

48 April Iflffll Ht^wliH I Pa('kar<I Journal 

)Copr. 1949-1998 Hewlett-Packard Co. 

Fig. 7. SAl^'D nitcnxin uil. 

across it, which is proportional to the incident outijut 
power. The dc vohage front Ihe diode is used liy Ihe ALC 
loop to provide improved o\itpiit pov^-^er flatJiess as a func- 
tion of frequency. Because of I iic bridge's directivity, the 
leveling circuit ignores reflections from the load and thus 
provides a good source match. 

Big. 7 is a photograph of the SAFD microcircuit. 

0,01-to-2-GHz Heterodyne Band 

The (}.01-Io-2<;Hz band in the III* 8:J752A/H sweepers is gen- 
erated by mixing 5.410 to 7.4 GHz ( ty j) from the DVt.) with a 
phase locked 5,4-GHz f f^p) oscillator in the hetero<iyne 
band mitrocircini. or HetBanfl fc^- shun. The heaii of I his 
ruicrtH ircuH is a(iii\s RFK/ mixer Fig. 8 is liie lieiBiiud 
block diagrajn. 

The GaAs RFIC mixer uses a doubly balanced FET bridge 
niijxer^ with on-chip RF ant! Li) i>liase sf^litting amplifiers and 
an on-chii^ (liffcreiUitil-to-single-ended IFautplifier. Mixer 
design considerations include LO and RF drive levels, signal 

purity, and port matcrh. Port match can be a problem at the 

sum and difference frequencies mid at the harmonics of fy ^ 
and f^f. Poor pon [Uatrh can cause reflecdons back into (he 
ndxer and degrade rhe level of spurious signals. Ulth a dis- 
crete mixer, perfomianee can often be dependent on assem- 
bly techniques. The GaAs RFIC mixer has buffered RF LO, 
and IF ports, making it inseusitive to Ihese assembly varia- 
tions. The bias on the FET l>ridge mixer is \he only critical 
adjustment. It was determined that for best performance 
over temperature, the mixer bias must be held to withui 
lO.OlV of its room-temperature setting. 

Measurements on the GaAs RFTC mixer indicated that there 
was some dependence of the 2-1 spiuious product (second 
harmonic of fftp i nixing with ff/> ) on the RF port source 
match at the frequency of the second hannonic. 10.8 GHz. 
Because if was desired to reduce the mixer's spurious prod- 
nets by controlling tJie harmonics at the RF utput, there is a 
fhiUtUz low-pass tiller at the HF port for this puq>ose. As is 
characteristic of simjjle low-pass fillers, the match at 10.8 
QHz is very bad, smce it is hi the stop band. The second har- 
monie generated by the mixer comes out the KF port and is 
re Heeled by the poor match of the filter 1*be second har- 
monic then re enters the mixer where it Ls an^pUfied and 
adds, in or out of phase, causing a vaiiation in ttie 2- 1 spuri- 
ous perfonnanee. An attenuator w^as added to the RF inpLii 
of the mixer to improve tlie source match and reduce die 
reflecdon back into ihe mixer Tiiis reduces the 2-1 spurious 
product to a low enough level lliat a filter at the IF output 
can reduce the level below the spurious specification. 

Amplitude modulation is done m the RF path. A broadbai^d 
stagger-spaced p-i-n diode modulator is used because a 
quaiter-W'ave-spaced modulator has less atlenuation at the 
second and fourth hannonitr frequeTieies. This ensures that 
there will be no increase in the harnionic levels through 
the tnodulation range, which would degrade Ihe spiurious 

The output power of the GaAs RFIC mixer is +5 dBm. The 
relatively high output powet^ from the mixer i equires less 
gmu from Ihe output anipliner Tlie lower overall gain re- 
(juircMuent results in a low level ofbroatlbLUMl noise, Ilie 
arlditional power ^u}d gain art^ provided L>y a new Gaj\s RFiC 
power imiplifier designed for this applieatiorr This IC is a dc 
coupled feedback amplifier designed specifically for bigti 

5 <l 1-10-7.4- GHz 






Ptiase- Locked 
bA-GHi Oscillator 







Mixer GaAs RFIC 

Power Amptrfjer 






0.01 10 2 


Fig. 8. HetBiiud riiK incircual tilock dia^mnu 

April Wm I Itvvirtl eac karf I .Iniiniiiil 49 

)Copr. 1949-1998 Hewlett-Packard Co. 

Fig. 9, Ht'iKatKl M.iirruLiM.:iiil. 

j>ower, gooti hamionicH, arui wide bajidwitkh. ESD protec- 
tion and a rt>inbinal ion liarmonk' and spnn(HJi> luw-piLss 
filter ate added \u d;e (nJt[>uL 

The niicrocircuit is constructed in a deep-well stairdess- 
si eel package using large 1 hick-film alumina ciiruil^ epoxy- 
attai'hed directly Iq the package IVmv (Kij^. y), Hiis eliinirmtes 
the need for circuh damps. A leUuritini copper heat sink is 
moniited irilo die package lltxji widi (Jie RFK' power fUnph- 
tipr niounled directly to lliis lieat sink. The heat sink extends 
out The back of the package and has fins for cooling ma- 
ehhied into it. Tliis combination provides the low thennai 
exiJiOLsion of stiiiiiiess stet*l kuid the higli them\al conductivity 
of copper. 

Coiubiner Modtilalor Amplifier 

Tilt* Mud Amp. shoi1 for c*>nibiner n^odulat or amplifier eonv 
bines the low-band ^md high-band signals from ibe ilual YUj 
oscillator (l)YOj und leciiiet Is them to Ihe lictHand or 

SAFD microcjrctjits. A signal is also sent to the sampler for 
phase !ockir\g. The MociAmp provides a pulse mmlulator and 
anipbt tide modtilation for the ALC circuit. 

The DYO has two outputs: a low band, 2 to 1 1 GHz, and a 
liigh btmd, J 1 to 20 GIlz. Each DVO output must be switched 
lo the buffer amplifier and musi be available at the sanii>ler 
ouiijut p<ii1. In acidition, the DYO low-band cnitput n^ast be 
switched to Ibe lJ.Ol-tO'2-GHz HetBaJul mic rocircuib 'Hie 
switch iiiitl coui)ler configuration Hie sliown in Pig> 10, the 
MocL\inp 1jIo( k diagram. The 11-t 0-20- GHz coupler is I he 
load for the 2-tod I-GHz coupler The advantage is tliat 
instead of having to design a 2-iQ^iQ-GH'i coupler, we need 
only two simjjier naiTCJwband couplers. If a single broad- 
band coupler were used, then there wouhl have lo l>e a 
switch at dic^ input to combine the DYO ontj>uts and a 
switch LLt'ter' the coupler to switch the output to Uie Het- 
Band. By using two couplers, one switch is eluninated from 
both the heterod^Tic path iuid the il-to-20-GHz path, thereby 
reducing the path loss in these two bands. 

A GaAs IC buffer amplifier is i)laced bet:ween the reflective 
ALC modulator and tlie DY(X This buffer prevents amptitude 
modulation resulting from the reflective modulatoi^s from 
entering the sampler port and causing AM-to-PM conversion 
in the samt^ler. The pulse and AiM modulators use the p-i-n 
diode nu)dulatoi:s dcvehjpetl pieviously/^ A high-pfiss filter 
between the two modulatru's reduces the cross lalk between 
the motlulators. Following Uie pulse motlulator is a gain and 
a power stage to drive the SAFD. 

The MocLAnip is built m a deep-well stainless-steel package 
widi 0,t) 10-inch sappliire mid almuina thin-film circuits €*poxy- 
attached threctly to dit^ package floor ( Fig. 1 1 ). The modida- 
tore tire placed in a:J-mm tiiannel fuacl lined into the package 
fioon The channels form a waveguide operating below^ cutoff 
to prcjvide the isolation that dee[> modulation requires. 

Ackii (iwledgnieiits 

For the DYO, the autiiors would like to tlumk .4ndy Smith 
for bis contnbution to die magnet design, Kiisti Rasmussen 
and Gai7 Gili)reTh for process development, Rick James and 
Jim (irlshaw h>r the Iow-i.jand oscillator development, Mi<:"bio 
Fiuiikawa, Dale Albin, and Andy Ilgward for i be higli-baiid 


Phase -tacked 




20 dB 






/ V 





Ta Heierodvfie 8aitd 
5.41 to 7 5 GHz 


Switcli A-^Pl-fier 

Ate Input 

Pulse Input 



V c V 

1 I 



2 to 211 GHz 




Fig. 10. MudAmp tTiicrof irciih block cliagram. 

50 April m03nfwlrti-PiU'kardJuMniia] 

)Copr. 1949-1998 Hewlett-Packard Co. 

f Igi. 1 1 * .>t'Ji i-TJ i 1 1 ' i i liL i. 'ijy A! ': liJii 

ostilliitor development, Doug Fullnier aiid Julio Perdomo 
for Ihetr work on the high-band GaAs IC; and Mike Sohigian 
and Arlen Dethlefeen for their guidance. 

The SAFD microciicuit wa-i niatle possible by the efforts of 
Jini Gnshaw, [Tiicrowave design engineer Andy Smith, me- 
chanical design engineer, Eric Rhiers, ALC bridge designer, 
and Lance Haag, systems engineer. 

For the HetBand and ModAmp microdrcuits, the oiechani- 
ca] design was done by Andy Smith and the new process 
development was done by Mike Shook, For the HetBand 
microcircuit Tini Shirley desired the GaAs RFIC mixer and 
power amplifiers and Pat Harper offered in valuable ad\ice 
and developed the production test process. 


1. G. Basawapatna aiid R. Standiff. "A Cmfied Approach w the 
Design of Wide-Sand Microwave SoUd-State Osciliatorsr IEEE 
Tivnsuction.^ on Micro^mtvc fltenrij and Techniques. Vol MTT-27, 
May 197fJ, pp, 37&-3a5. 

2. J, HeisK^n, Y7G Resonntois and FUtrrs, John Wapy and Sons^ 

3. AlIL Koenig, "A High-Speed Micro wa\e l*ulse Modulator," 
HewleU-Piu'kurd Journal^ Vot 42, no. 2, AprU 1991, pp. 34-36. 

)Copr. 1949-1998 Hewlett-Packard Co. 

April 1 lim I W w\i}\ t -Viw kard J t >iin ifiJ 5 1 

A Programmable 3 -GHz Pulse 

This new one-or-two-channel pulse generator provides precise edge 
placement, extensive functionality, and an interactive user interface. It is 
designed to help characterize and debug CMOS, ECL and GaAs devices 
and signal integrity problems. 

by Haas-Jurgeii Wagner 

A inEyor tjend for the c^oiiiputer tmd corTiiriiini cations Indus- 
tries is the need to [jrocess more ajid more data in less atvd 
less time. Tliis impels designers of digital devices tor these 
industries to develop faster and more t^omplex devices. For 
example, the clock speed of CMOS microprocessors has 
increased by a factor of two every three to four yem's. De- 
signers are expected to achieve these higher sfieeds while 
maintaining system reliability and reducing the j>rice. This 
often means thai for a given tecimology, processes may be 
driven to their limiLs, and the problems faced by designers 
of digital devices may be analog problems, T^i^qjical of such 
problems aie crosstalk, bandwidth lindiatiuns, ground 
bounce, jitter, reflections caused by misniatt'hes, pattern 
dependencies, and so on. 

Tlie HP 81*J^A pulse generator, Fig. 1, is designed for cus- 
tomers who have to characterize and debng these signal 
integrity problems on the bent !i or in a test system with a 
sampling oscilloscope as a t esi>onse unit, Ftist CMOS, ECL, 
and GaAs devices can be stimulated by the HP 8i33A, which 
nms at clock rates up to 3 GHz iii single-chartnel or two- 
chamiel configiu'afions (up to six eliannels v^idi an accessory 
kit). Mju'gin testing, worst-case testing, device characteriza- 
tion ajid debuggingj and analysis of signal integrity problems 
are ty|)ical applications, Bg. 2 shows typical waveforms that 
can be generated by the HP 8 133 A. 

The key contribntions of the IIP 8133A are its precise edge 
placement J it^ extensive fimclionality, and its interactive 
human interface. Precise edge placement is achieved by ftist, 
fixed transition times ( < 100 ps, itM to 90)6), very low jitter 
( < 5 ps rms), fine timing resolution (1 ps), and stable edges 

regardless of parameter settings (delay accuracy < 150 ps, 
width accuracy < lOt) psj. The small j liter and the fme reso- 
lution ill low. for exaJtiple, characlerizatlon of tl;e nietastabil- 
ity of a fltp-flop. The typical jitter of Jess titan 2 ps results in 
a i>eak-to-peak jitter of about 12 ps. Thus, measurement 
resolution of 10 ps is possible vrithout averaging. 

The functionahty of the HP 8 133 A pulse generator includes 
programmable pulse amplitutiej offset, deiay» width, and 
repetition rate. Table I sfiows the parameter ranges. Atkli- 
tionaliy, a<(justable phase and skew alkrw the iiustmment to 
address multipiiase clock applications without an external 
controller. The squai'e mode offeiT* a 50% duty cycle with 
variable frequency. The haidware architectiu'e allows acyust- 
ment of the delay parameter over its entire range at any 
frequency; for example, at 1 Gllz, ±5 periods of (ielay are 
available. Also, the width parameter does not suffer from 
£my recovery rime limitations as it does in traditional pulse 
generator Jirchitectures. The trailing edge can be moved 
anywhere withiti the period, limited only by the instrument 

Second Channel Options 

For the optional sex/onci chamiel the customer can choose 
either a second pulse cJaannel or a pulse/data channel The 
second pulse chaimel offers the same parameters as the first 
chaimeL In addition, the frequency of this channel can be 
divided by L 2, 4, 8, 16. 32, or 64. Thus, the two chaimels can 
run at different frequencies, wliich is important for testing 
the setup and hold times of fhp-flops, for example. 




■ a B 03 a 

1 " A 8 O S j 



.. T".. 






E 1 1 




4, A ^ 


it ^ p 

Fig, 1, The HP S133A pulse 
grn^rator provides pulses \\ith 
repel itioii rates up to 3 GHz. AO 
jHi Isp paj'ameters are accurately 
prngraininable. An optional see- 
om\ L'haruiel can be cither a puLsc 
charinc] tjra pulse/data channel 
capable of generating a 32- bit 
data vvord or a psieudurandoni 
binary sequence. 

52 April ] im Hc^wlett-Pat'kard Joiimnl 

)Copr. 1949-1998 Hewlett-Packard Co. 

Pf«<;isian Ed§e Placement 

Ch 1 = 500.0 mV/div Offset ^ O.OOOV 

Time Base = 200 ps/(fiv 

Noise Iminunity — Spikes 


hHEr-Phsse Clock 




Cit. T = 300J mV/div Qffsel = 1.5(K3V 

Ch 2 = 300,0 mV/div Offset - asoov 

Time Ease = 50Q ps/div 

GJi. 1 = 3.IK»V/div 
Ch.2 = 3.{IO0V/div 
Di. a = 3.«XIV/div 
Ch. 4 = 3.a00V/div 
Time Base =: 2S0 p^div 

Offset = ~1S0QV 
Dflset = -1.500V 
Offset = -1 ,500V 
Oftee!^ -1.500V 

32-8)1 Pulse Stream 

",— V 

T^- f^"'^"**"^*^, 

S-!rf «»i-N».. 

■-kgj ^, 

«. Vl^. _ _:iflf*-' . SN»i '-ri 

ijt ' 



!- ^ 1 

.^ 1 * f ' ■ 

\ \ 

U». V 

!■ 'H 

£v& OJagrioi 

Ch. 1 = 5O0.0 mWh Offset = -Z.500V 

Cfi. 2 = 5O0.O mV/div Offset = -2,50aV 

Tune Base = 1.00 ns/div 


X "^X 

C h. 1 =^ 500.0 m V/dJ V Offset ^ O.OOOV 

Time Base = 100 ps/rfiv 

Fig. 2. Examples of HP S133A 
pulse generator OLilput wave forms 
displayed on a di^taJ oscilloscopes 

Table f 
HP 81 33 A Pulse Generator Parameter Ranges 

Repetition Rate: 32 MEz to 3 GHz 

Delay: -5 ns to +5 ns (-5 ns to + 15 ns, square niode only) 

Width: 150 ps to 10 ns 

Amplitude*: 300 niV lo 3V pp into 50 ohms, 600 mV to 6V pp 
into an open circuit 

Oulput Voltage Window: -ZV to +4V into 50 ohms, ^V to 
-hSV mto an open circuit 

THgger Out Amplitude: 0.5V pp to L8V pp into 50 ohms 

Tiigger Out Voltage Window: -4V to +4V 

The pulse/data channel offers a sijuare wave mode, a 
progranunable 32-bit pattern, and a jiseudorandoni binai*y 
sequence (PRBS) of length 2P - I bits. The sqnare wave 
signal can be divided by L 2. 4, B. 16, or 32. The 32-bit pat- 
tern is useful for testing tt^e pattern dei>endent settling of a 
GnAa line tlriver or a chain of EC L gates with (iiJTereiU rise 
and fall tintes^ for example. The PRBS makes it pos,sible to 
generate aiT eye diagram that shows the noise, timing and 
bandwidth problems, and margin.s of the deviee under test In 
a single picture. The design of the pnlse/data channel is 
discussed in the article on page 56. 

The trigger tHitpnt is a programniai>Ie square wave signal. 
The triggtT frequency can be divitled by 1, 2, 4. B, 16, 32, or 
64, This makes il possible to trigger an oscilloscope even if 
the oscilloscope has a limited trigger bandwidth. It can also 
improve the jitter iierff^rrnatue of the meiisurement. The 
prngranuiiable onlt>ul amplitude of up tt> l.BVpp allows the 
ust* of a ptiwer splitter tu get t wfj BCL signals, one to trigger 
the oscilloscope iuul the second for the device under test as 
a third pulse chatuiel. 

In the external clock mode the input frequency can be di- 
vided by If 2, 4, 8, 16, 32, or 64. In a master/slave four^hannel 
configuration the slave can run at a divided frequency. The 
input frequency is measured and displayed, and the phase 
and duty cycle parameters are programmable with the same 
acciu'acy as in internal mode; no external controller is 


Fig. 3 shows the block diagram of the instnunent for the 
different twochaiuiel contigu rations. The interconnection 
between the timing board mid the two output chamiels is at 
the real' panel so that additional delay lines for each channel 
can be added. This is useful in a multichannel master/slave 
configuration (also shown in Fig. 3) to deskew the output 
channels of the master compared t,o the output channels of 
IJie slave. 

For each functional block we tried to find the lowest-cost 

technfilogy that fit our ni2inufarturing process and tiiet the 

perforniant^e goals witli sufficient margin. The tectmo logics 


IC Processes 

E( 'L programmable counter ASIC 

FCT. multiplexer ASIC 

ECL sequencer/PRBS gate array 

Si pulse foniiatter 

GaAs output amplifier 
Hyl>rid Processes 

Analog delay thick-film hybrid 

Switfited delay thin-film hybrid 

Outjiut amplifier Ihick-film byl)rid 

Pulse formatter thick-film hybrid. 

)Copr. 1949-1998 Hewlett-Packard Co. 

April Umd Hov-'lert-f'Jit'kitrfi ,lciurJi:JJ 53 


Channel 1 

Extern at 
Dlock \n 






iiTO Trigger 

Channel 2 

Channel 2 


Opt 003 

Channel 1 





Channel 3 

Channel 2 



Chani^el 4 


Fig. 3. T\vo 1 wocharaiei HP B133A pulse generators in a foui-channei master-slave corJiguratlon. In the lower instnmient diaimel 2 is a 
pills p f hanne! like chaimel L while in the upper instrument channel 2 is a pulseidata channel. External dplay lines compensate for timing 

skew between tlie uutpul c'liannels of the two instruments. 

Printed Circuit Boards 
Standard FR-4 HP boards, surface mount components 
Discrete shaper amplifiers {GaAs FETs} 

^ Citstoniized semiiigid ini ere onnect ions 

Design details of the various functional blocks of the 
instrujnent can be foimd in the article on page 60. 

User Interface 

The interactive human interface allows direct access to each 
pulse parameter with the press of a key or tw^o. The front 
panel antl user interfile e w^ere developed with the foUo^vIng 
m^or goals in mind: 

5 4 April I *M3 tkw ! v\ t- r*ackiin1 Jrm mul 

)Copr. 1949-1998 Hewlett-Packard Co. 

Make the HP Sia3A "^Icxik and feel" like an HP 8K30A or 

813 1 A pulse generator 1 to show that they belong to the 

same faniiiy of pulse generators and to niake it e^sy for a 

user who is famiiiar ^ith the HP SI-30A/31A to work with 


Enhance the parameter display. 

Make it quick and easy io change parameters. 

Allow the user to focus on the device under test while 

varying parameters. 

Parameter Display. After experimenting with different display 
modules, we decided to use four S-character 5-by-7 dot ma- 
trix LED display modules, which offer several advantages. 
This arrangement rati disi>lay iwo parameters at a time i^ith 
their names and miits. It can display a gra|>hic representa- 
tion of the 32-bit data word of the data chaimel using the 
nser-deOnable chaiact er feature of these modules. It can 
easily highlight the current j^arameter using the software- 
atljustable brightness feature of tiie display modules. It also 
has the desired look, close to that of the HP 8130A/31A. 

Keyboard and LED s. For the front -pane I keys and LEDs, we 
decided to stay as close as possible to the HP S130A/31A. We 
use the same keys as in the HP S130A/31A because they are 
known to be reliable ( although relatively expensive). The 
LEDs have sunilar meanings to ttiose in the HP 8 130 A/31 A. 
LEDs In the keys show tlie ciunrently selected paiiuneters, 
LEDs above the keys show which of the tw^o parameters or 

modes that this key represents is selected. All parameters 
are accessible through one or at most two key presses. The 
operating modes of the instrument can be seen at a glance 
without switching display pages. 

One conceptual change was made. Tlie vernier keys behave 
differently than m the HP Sl-^OA/^J J A. There are no range 
keys, and there are five pairs of up-down kej^ (instead of 
three). Each vernier key has a fixed delta assigned to ir — 
depending on the parameter, of course. The advantage is 
Ihat each pre^ of a vernier key causes a constant inc_renient 
or decrement, unlike the HP S130A/31 A, where the incre' 
ment or decrement changes with the range of the parameter. 

Error Behavior All parameters can be modified virlthin their 
hard limits, whether or not I hey generate a conflict with 
other parameters, such as wirftli greater than period or higli 
level less t han low level. In case of such conflicts, the user is 
directed out of the error state with a full-text error message 
and a flashing arrow in the display that indicates in which 
dii-ection the parameter must be modified to resolve the 


1. W. Berkel, et al, "500-MHz and 30^MI!z Programmable Pulse 
Generatt^rs," Hevk'tt-Prnkaf^ Jovnml. Vol. 41, no. 4, August 1990, 
pp, 64-78. 

)Copr. 1949-1998 Hewlett-Packard Co. 

Ap ril 1 \m I ie w loli I 'iiv karrt .Jo ii mn iJ 55 

Pulse/Data Channel Extends 
Programmable Pulse Generator 

This optional second channel for the HP 8133A pulse generator has a 
dividabie square wave mode, a 32-bit data burst mode, and a pseudo- 
random binary sequence (PRBS) mode. Its major components are a data 
gate array, a multiplexer, a phase-locked loop, and an output section. 
Most circuits are ECL 

by Christoph Kalkahl 

The HF 8133A 3-GHz pulse generator is a\^aalablc in single- 

channel and two-nliaiuiel configurations. Two options are 

available for cliaimeJ 2: a second pulse channel like channel 1 

or a pulse/data channel. The? piilstVdata channel is designed 

to offer some additional features: 

A square wave that can be divided by 1, 2, 4, 8, 16, or 32 

A r32-bit data palteni that can lie edited 

A pseud orajidojxi binary sequence (PRBS) with a length of 

2^'^ - 1 bit-s, according to CCITT recommendation 0.151. 

Fig. 1 shows waveforms from a pulse ehmmel aiul a pulse/ 
data chimnel illustrating lite divided square wave capability. 
The pulse/data chaj^nel (channel 2) is gen€>rating a square 
wave at half t he frequency of tiie pulse train generated by 
channel L Figs. 2a and 2b show^ pulse/data channel data 
pati.enis in RZ (return to zero) aud NRZ (nonretiuri to zero) 
data formats. Fig. 3 shows a PRBS eye diagram wit!i sarn- 
pling clock. The data format is NRZ ;is in most applications. 
The PRBS is also available in RZ fommt. 


The square wave mode ad<lresses applications in which a 
clock signal is needed. The <Uvjded square wave is useful 

j ■ i 



1 , V... J..,,„i,, 







,../, ■■ 

, .\ 




^ _ ^ / 

Ch. I = 500.1! m/ifiv Offset ^ t.OQOV 

Ch. 2 = 500.0 mmiv Offset = I.OOOV 

T^me Base =r ZSO ps/div 

Fig* 1. Chaiuiel 1 flop): Normal pulse output. Channel 2 (bottom): 
diwied square wave at 50% duty cycle and half the frequeney. 

lor testing llip-fiops or for applications that require multi- 
frequency dock signals. 

The 32-bit data mode provides repetitive bursts for use with 
an oscilloscope. The settling behavior of amplifiers aiid line 





^ r 







\' ' 'it' '<■ 


.. 1 r -^ 1 ,. , ,. 


^^^ J 


1, ^ , ! 


U- ► 

1 ^- 

1 1 h-^i^f ,11-. 


' '1' - 

1 1 


1 c 

-J it— -tart— 



C h . 1 = 500.0 m V/d iv Offse* = -2 JOflV 

Ch. Z = 5(30.0 mV/div Offset = -2.50&V 

Time Base = 1.00 ns/div 


, .J. . 

' 1 

1 l| r • 

Eww^- ■ 

1 1 

1 iJ' - 








1 ' ' 'j 


.^1 ,r.r 



i : 1 :: 

Ch. 1 ^ 500,0 ntV/div Offset = -1500V 
Cfi. 2 - 500.0 m V/tf rv Offset = -2.500V 

Time Base - 1 ,00 ns^div 


Fig. 2. Channel 1: Normal putse output. Channel 2: (a) RZ (return 
to zero! datapatteni. (b) NRZ (nanretuni to iero) data patteni. 

56 Apiil imn TTewIptT-Pafkard JoumaJ 

)Copr. 1949-1998 Hewlett-Packard Co. 



Ch 1 =^ 5OO.0 mfdvi Offset = 1.IIQ0V 

Gh, Z - 50a.Q mV/div Offset = lOOOV 

Time Base = 250 ps/div 

Fig. 3. Cliaimel 1 : Siiitipling clock. Chaiuiel 2; PRBS eye diagmrii. 

receivers can be seen with some bits set to I and the rest set 
to U. Editing of the pattern is Quick and easy, A rotate fea- 
ture scrolls the pattern through the oscilloscope screen. 

Fig. 4 illustrates a meastirenient of the nietastabilit\' of a 
flip- Hop. The picture shows the clock signal C, the data 
uiput D, and the output Q of the flip-flop. C and D are moni- 
tored at the input of the 1)1 'T (device under test). The transi- 
tions of the pulse generator have been slowed dov^Ti by tran- 
sition-time converters (HP 15435A, 150-ps transitions) to 
avoid pulse distortion by ttie capaeitive load of the flip-flop 
inputs, Metastabihty is caused by violating ihe setup km6 
hold tunes of the flip-flop. Clocking the flip-flop exactly on 
the edge of I) sets the flip-flop to a metastable condition. 
Thus, the melaalabillty can be used to find the samphng 
point of the fli|>-nop and the corresponding D-Q timing rela- 
tionships. Tlie time window wheie the metastability occurs 
is very narrow — about 2 ps. IF the clock C moves only 1 or 2 
ps lolt or right with res])et't l.(.) D, the metastability will dis- 
appear. For this reason, this is a very cliffioull [Ueiisiuenient 
to make, and the fast slopes, accurate timings and low jitter 
of the HP 8I.'33A are essential. 

The purpose of the PRBS feature is not primarily for use 
with a bit error rate tester (BERT), although it will work 


Ch. t ^ HW.g mV/div 
Ch. 2 = 50a mV/div 
Ch. 3 = SOO.a mV/div 
Time Base = 500 ps/div 
Delta t = 2Q,Z ps 
Si art = 22 5026 ns 

mf set = -e4D.a mV 
Offset = 750.0 mV 
Offsel = Z,Z90V 
Delay = 212900 ns 

Stop = Z2.5234 ns 

Fig. 4, Mriast ability oj u nip-llt)|j (Channel 1 (tup): Flip- flop rjix k 
inpui. (.■haiiiiel2 (nuddle); KtliJ-flo]) U input, (tjottoinj FHpflop (J 


well and provide excellent pulse performance. A very bnpor- 
taut application is die characierization of high-speed de- 
vicea To a user with a litde experience, the PRBS can show 
all of the i^roblenis of a circuit In one picture, since it con- 
tains multiple frequencies and dutj^ cycles. Bandwidth prob- 
lems within a circuit tliat are hidden by faster circuits down- 
stream in the signal path cause increased jitter, for example. 

Block Diagram 

Fig. 5 shows the block diagram of the puiseMata board. Tlie 
square wave clock signal from the timing board is refreshed 
by a shaper amplifier. A 4: 1 multiplexer (MlIX) adds the data 
information and determines the data format (RZ = return to 
zero, NEZ = nonreturn to s&ero). The signal then goes to an 
output section kienticaJ lo thai of the stimdaid pulse chan- 
nel, consisting of a GaAs amplifier with support ciix-uits and 
disable relays. 

Tlie multiplexer receives the data bits from the data gate 
array, which contains the bitstream sequencer and a hard- 
wired PRBS generator This gate array, which is leveraged 
from the HP SOOOOA data generator, Itas a maximum operat- 
ing frequency of 1 GHz. Tlie data memory cor^sists of simple 
(low-power) static latches, which contain the programmable 
1^2-bit word. The PRBS generator outputs four (2-^^ - l)-bit 
PRBS bitst reams at one-fourth the clock rate which are mul- 
tiplexed together to form the fmaJ (2^-^ - D^bit PRBS hit- 
streani. lite data gate array also generates a frame signal to 
mark the start of the 32-bit word. 

The bitstreams between the data gate array and the multi- 
plexer must be s>Ticluonizcd. Since the data gate array has a 
propagation delay of severed nanoseconds, the clock for this 
device has lo l>e early by this amount with respect to the 
CtK/4 referejice out.|)Ut of the multiplexer This negative delay 
is realized by a t>hase-locked loop (the negative delay is only 
possible in repetitive applications). 

The phasf '^locked loop consists of the conmion functional 
blocks: phase detector, loop filter (or rc^gulator), VCO 
(voltage-t^on trolled oscillator), and frequency divider The 
V( ■O lias a one-octave range (50t) MHz tcj 1 GHz), and lower 
frequeucies are produced by division. The feedback and 
reference paths are divided by 16 because of the frequency 
limit tjf tlte phase detecior A hnut-and-detect circuit ensiu^es 
proper control voltage foiuiitions ff>rthe VCC), This circuit 
detects tlie end of a trequeiicy range iiiid ger^erates an inter- 
rupt. Details of the phase-locked loop are discussed below 
and are shown in Fig, 6. 

A temperature sensor measures the chip temperature of the 
data gate array This is necessary for delay drift compensa- 
tion in the gate anay. Ilie temperature drift of die gate array 
j.s compensated with internal ac^justable delay lines. 

The frame marker signal goes through a retiming circuit to 
avoid interna] synchronization jitter on the trigger signal 
(which can occur ui tlie phase-locked loop). The output sig- 
nal (jf this retiming circuit is internally called STR08E but is 
actually die trigger signal in BITO trigger nuxle. Jitter on tiiis 
trigger would cause a jittery display on the oscilloscope even 
when the output signals are clean- The delay circuit ahead of 
the rt^timing circuit is lised for delay drift compensation of 

Ap ri 1 1 t)Ej;i tt p wl<?t;t-Packard Jouma] 57 

)Copr. 1949-1998 Hewlett-Packard Co. 


Delav Line 


DpFay Line 

to Timing Saard 



B.5 to 

OS to 


i ! 
-\ r- 





Relay sou 


Clock from Timing Board 

DBI = Device Bus Interface 




Amphlprte Offset ^^^^^^ ^^^ 

Relay <' 




Fig* 5. Block diagram of the optional piilse/data board for tho HP 81;1.'^A pulse generator. 

the frame marker signal over lentperature while cf>nipensa- 
tioii of the Di, D2, 03, aiitl 04 gale tirray output tiaUi fharinels 
is handled by inteiTia] a^yiLslable delay lines in the data gate 

Phase- Locked Loop 

The phase-locked loop on the pulse/data board generates a 
negative delay of 12 ns. This negative delay is required l>e- 
cause of the inlen^al delay of the data gale array as nien- 
tJoned above, A^s shown in Fig* 5, the loop refeience is the 
clock/4 (CLK/4) output of the 4:1 multiplexer (MUX). The 
loop output to the data gate array is one of tl\e two outputs 
of the programmable frequeuey divider. 

The demands on the performance of the phase-locked loop 
are severe. \i must work tiver a 7-octave range with high 
phase accuracy and h)w synchronization jitter At liigh fre- 
quencies, jitter iind linung accuracy are the mam concerns, 
while phase accuracy becomes important at low frequen- 
cies. The timing window at a clock frequent y of -3,2 GHz is 
L25 ns (clock divided by 4). Setup aiuJ hold times, jit ten and 
delay deviations (only 2()0-ps steps are possible in t fve data 
gate array) must fit within this v^indow. 

By factory calibration the data acquisition point (the time 
when the signals on the data lines aj^e considered valid and 
can be sampled) is set to 650 ps (half the peiiotl al the high- 
est frequency) after an mtenial data transition. Tlius the 
time froni the data transition to the acquisition point remains 
nearly constaiu while the time from tiie acquisition point to 
the next data transition is longer at lower frequencies. At 
low frequencies phase accmacy becomes important. 650 ps 

is only al)om two degrees of phase error at the lowest fre- 
quent y ( CU/4 = 8.25 MHz). Tltere is a high risk that errors in 
timing could occur if the phase were to lag only a few de- 
grees. Tlierefore, a prephase shift is huiit hi. which shifts the 
data transitions ahead at all hequencies. A few degrees are 
enough, but the direction is very important. The absolute 
amount of the prep base shift depends on the individual 
hardware cUid is rnejisured tiuring internal delay calibration. 

Dividers. The loop phase detector has a m^iximimi operating 
frequency of 80 MHz, while the CLK/4 signal is between 8 Mliz 
ajKl 800 MH^ (at im instmment frequency of 32 MHz to 3.2 
GHz). Therefore, the reference ;md the VTO output after the 
programmable frequency thvider luive ttj he divided hy 16. 
These dividers consisi of ECL D-type flip-flops. TVvo ICs are 
used, each containing four nip-flo|:>s (16 = 2"^). However^ 
instead of tlie VCO signal path goirig tlirougli one IC and the 
reference path going through the other, both paths go 
through both ICs and are divided by four in each IC. The 
advantage of this arrangement is better matciiing of die tem- 
per atiue dependeiU tielays in the two patlis, at the expense 
of a slight incrciise in cross talk. 

Negative Delay. The effect of the loop and phase detector is 
to cause the divided VCO output to track the reference input 
with zero phase difference. The required negative delay be- 
tweej\ the refereiu'e and the divided VCC) output is produced 
by a delay line in the loop. The delay line is placed iifter the 
dividers to reduce the influence of cable loss, which 
increases at higher frequencies. 

58 .\pn\ 1 993 Hpwlett-P&ckai?d Joiimal 

)Copr. 1949-1998 Hewlett-Packard Co. 


vV # # 

Gain Switching 


< B5 He R7 He 



V V V ▼ V v'V 



D Hlur 4tW 

a;7 C4 >*? 

Lmel Shift 

0.47 to 1.05 GHz 
Input C = 10 nF 


, To Frequency 
\f Diviiler 



Ca B22 

Add Prophase 





Fig. fi. PhaKelo^^kocI iijop clptiuls. 

Phase Detector The MC 12040 phase detector is a digitaJ 
pliase-aJtd'fre(iuency-i5ensibve ECL t>pe witli a maxliiiuiu 
operating frequenfy of SO MHz. it must cover a 7-octave 
range aiid not locrk on hamionics, which would cause un- 
proper range detection, I^oper t.ermmation of both Input 
lines is important because of the fast slopes. The phase de- 
tector produces four outputs fU, 0, D, U) wl^ich arc cross- 
wired fU to U and D to D) for temt>eralure convpensation of 
the ECL output levels, which have a strong influence on Ihe 
phase error. The resulting two outputs go to the loop filter 
(see Fig. 6). 

Loop Filter. The lii-st .stage of the loop filter is a symmetrical 
low-pass filter consisting of Ri to R4, (*i, and Cy. The Iblkiw- 
ing stage is a comliination of an instnnnenlation iunpIifieT 
(consisting of lluee o]>eratioriiil mriplillersj imd a PI (propor- 
tional integral) regulator. Range switctiirtg of the prograni- 
matiie fretiuency divider requires related gain .switcliing of the 
fdler, which is realized by varying the gain-controlling resis- 
tors and a switchable double-T attenuator. This tlesign was 
chosen for its low^ dc offsets (which catjse phase error). An 
earher, nonsymmetrical design, using a DAC for attenuation, 
had unacceptable dc offsets. 

In the first stage of the loop filter, a sUght offset Ls added by 
resistor R22 to achieve the prephase shift discussed above. 

The phase detector has ECHevel outputs (the 50-ohm ter- 
minators to -2V are not shown ui Fig. 6). so the average dc 
level at the + inputs of die symmetrical operational ainplifl' 
ers is about -L3V. Thus a ciurent is iryected from ground 
tlirough R22, 

The syimnetric!al PI regulator has a level shifter at its output 
so that the operational amplifier has a higher margin to the 
po.siiive limit of its output. The limit and detect circuit limits 
the VCO tontrt*! voltagt^ window and detects when the limits 
are reachetl. A serial resistor betw^een the loop filter and 
the VCO forms a low-pass filter with the 10-nF VCO input 

Oscillator and Frequency Dtvider. The oscillator is a varactor 
LV tyije. A resistive attenuator aiifi a ijlocking capat^itor 
adapt tJ[e output to ECL levels for the progranmiable fre- 
quency divider. The programmable frequency divider Ls a 
high-speed ECL ASIC that permits di\ision by 1, 2, 4, S, 16, 
^^2, or 64. One of the outputs is used to close the loop while 
die other feeds the data gate anay with Uie negatii^ely 
delayed signal. 


1 would like to thank Thomas Thoet, who designed the data 
gate array 

)Copr. 1949-1998 Hewlett-Packard Co. 

,^p til I m^ r li' w I V I xViKkard , I uuni m| 59 

Design of a 3-GHz Pulse Generator 

Period, delay, and width generation for the HP 8133A pulse generator 
depend on several thick-film and thin-film hybrid circuits and custom GaAs 
and bipolar ICs. The high frequencies and fast transitions made radiated 
interference suppression challenging. 

by Peter Schinzel, Andreas Pfaff, Thomas Dippon, Thomas Fischer, and Allan R. Armstrong 

This article discusses the internal design of the IIP 8133A 
3-GHz pulse generator (see article, jDage 52), including the 
linimg boards the width board and output amplifier, and tlic 
EMC design. 

The timing board generates tlie basic pulse train of tjie 
msfniment witli prcjgrainiiiable pulse rept-litinr^ period (or 
equivalently, hetfuency ). Its niputs are tlie external clock 
signid, if iuiy, tuid the STROBE signal from the pulse/data 
boartL if installed. Its out|Juts are a delayed or undclayed 
pulse output W l\w width ijoard {depenfling on the instRi- 
ment option), a dividable pulse output to ihe pulse/data 
board, a tiigger output to the front panel, and a divided 
clock signal to the processor boiird. The main goals were 
timing resolution of I ps for pt^riod and delay, jitter less thmi 
5 ps rms, and frequency accmacy better than 0^6%, Fig. 1 is a 
biock diagram of tlie timing boai^d. 

Period Generation 

Because very low Jilter and liigh stability were m^or goals, a 
YIG oscHialor is used kis tlie main iimii^g source of tire inslru- 
meni* The YIG oscillator frettuency is programmed between 
2 GHz and 4 GHz by a i2-bit DAC to achieve a period resolu- 
tion of 1 ps. To achieve low jilter a special reference groinid 
likme for the circuil (hat <lrives the YIG is integrated on the 
l^rinted cireuit board to avoid noise ajid cross talk between 
the YIG driver aiul tJther con^por^erUs. To reduce the noise of 
tiie YIG driver further, the baiid width of tJie driver compo- 
nents is reduced almost to the fastest programiuing speed. 

When tiie instniment nans below 2 GHiJ the YIG oscillator 
sigual is tlivided by two by a static GaAs divider. For output 
frequencies between 2 GHz and 3 GHz tiie divider is by- 
passeci by tw^o GaAs switches (switch 1 and s\¥itch 2 in Fig, 
1 ). This additional division by two is necessary because the 
programmable frequently divider used to generate frequen- 
cies down to 33 MHz operates at input frequencies only up 
to 3 GHz while the YIG oscillator frequency can be as high 
as 4 GHz. 


2 to 4 GHz 


- r to 64 



Delayed Outpyi 
to Width Board 

Svwitchi SwifcltZ 

Switch 3 

External Clock 




Undclayed Output io 
Pulse/Dala Soard 


Amplitude O.ZVto+1.8V 
Offset -19V10+3.9V 

Trigger Output 
to Front Panel 

Switch 4 


Switch S 

Switch G 


To Frequency Coufiter 
on Processor Board 

Fig, 1. Block diagmm of the timing board of tlw HP 8133A pulse generator. 

60 April 1993 Hcw!mi-PackartJ Jouniid 

)Copr. 1949-1998 Hewlett-Packard Co. 

Cooling of the Frequency Duider IC 

For the timing board of the HP 81 33 A puEse generator, surface motjnt technology is 
umd to attadi the components to Itie boanl The frequency drvidtr IC has a spe- 
cial pacl^ge (The multiplexer on the pufse/da^ board has a siinifer package.! It is 
a cyhndficai ceramic housing wfth 24 radial ieads. The leajsare located around 
thecy'iricler hattway tietween the top an6 the bottom (see Rg 1 1 Therefore, a 
hole is requiied in the pnnted circuit boanJ for the bottom half 

The power consumption of the iC is 2.5W. Because of the smaf] sue of the pack- 
age {bJ mm dtameter}, efficient cooling with a heat smk is necessaTv However. It 

is not possible to giue a heat sink on the bottom half of the package where the 
chip IS mnuniBd because the leads could be damaged by shock or vibration, and 
the IC would nGt be exchangeabfe because the ieads would be abev^ the board 
and the heat sink beJow the board 

Another problem is the printed circuit board. The thickness of the board is 1 .6 mm 
and the tolerance is ±10% The solder process also has a tolerance in the thick- 
ness of the solder area. These toierances have to be sccammodated by the heat 
Sink design and the mounting of the components. 

The solution we used m the HP 8133A pulse generator is shown in Fig. 1 . The 
prescaler IC is soldered to the surface of the printed circuit board. Above the IC 
package a spring is mounted. The spring is a sheet-metal part made of spring-tem- 
pered bronze ICu-Sn alloy) and has a thickness of 0.6 mm A spacer is pressed into 
the spring. Together, this spacer and the package above the printed circuit board 
are higher than the two spacers beside the IC, so the spring is always slightly 
p reloaded. Between the spacer on the spring and the top side of the package is a 
thermally conductive foil that isolates the package from the metal parts to prevent 
electrical coupling. 

Under the printed circuit board is a milied heat sink with two threaded studs 
pressed into it. The spring and ihe spacers are mounted on these studs. The nexr 
step in mounting the assembly is to screw the M6 screw into the heat sink The 
screw is brass for good thermal conductivity and has a flat point. The mounting 
has to be done with the minrmum possible torque (optrmal would be zero torque! 
to avofd breaking the ceramtc package. Between the flat end of the screw and the 
bottom side of the package is a thermally conduclive foil like the one on the top 

The last step m mounting the assembly is to mount the printed circuit board on the 
board shield. The heat sink is screwed to the board shield with M3 screws and 
M3 plastic shoulder washers for electrical isolation. The msulator sheet between 
the board shield and the heat sink is a thermally conductive (oil that provides both 
thermal coupling and electrical isolation All o( the thermally conductive foils are 
self-adhesive for simple mounting. 


Priifted Circuit 



Dividef IC 

Sntd PresS'iit M3 

Heat Sink 


■ Insulator Sheet 
Scr«w M6>^fi 


InsyJator Slieet 

Board Slileld 

Ptastic Washer Ml 
Screw M3 

Fifl. 1 Components for mounting and cooling the frectuency divider IC en th« timing board of 
The HP 8133A pulse generator 

The board shield and the pnnted circuit board are also joined with additional 

spacers and other heat sinks The board shield has different functions: it is used 
as a heat sink, as protection against board damage, as an electrical shield, and as 
a guide for the board in the cardcage. 

Thomas Fischer 
Devefopment Engineer 

Btiblingen Instrument Division 

The programmable frequency divider is a bipolar ASIC, Its 

key specifications are; 

Input fretjuency range: dc to 3 GHz 

Division facton 1^ 2, 4, 8, 16, 32, or 64 

Output levels: ECL, differential 

Input sensitivity; 200 mV pp single-ended, 100 mVpp 


Afler tlie rrefiuency divider, the signal is .s[jlit into a delayed 
pSilh and an uticlelayed pattt. llie delayed sigruil goe.s through 
a delay block, while the unilelayed signal goes (h rough a 
second progranunable divider thai <1ivides the pidse/data 
output by 1, 2, 4, 8, 16, -32, or *>1. AiH>lbt^r prograrurttable 
divider is Integrated in the trigj^er pal h so the trigger can 
als(* be divided t>y l, 2, 4, B, 16, 32, or 64, Tills feature makes 
it piosslble to trigger an (jstilkjscope when I he instrument is 
running at :] GHx, even it the trigger cjrciiii of rhe oscillo- 
scope does not W(>rk ui) lo 3 GHz. Dividing tlu- trigger out- 
put when dip instmnient is running at high fr«iuencies gen- 
erally impn>ves the trigger perfonnatue of the o?sfrilk>srr>pe. 

Jitter is reduced and edge placement measurements can be 
made more accurately. 

If the instnimenl is running hi the data mode the trigger is 
synchronized v^itti (he data on lite ptilse/data board (see ar- 
ticle, page 56). In this mode the STROBE signal from the data 
board is switched into the trigger path by switches 4 and 5. 

Tlie trigger output antplifier is a shaping amplifier, which is 
described in detail later. The trigger output is progranunable 
in ^unplitude (200 mV to 1.8V) in a ^V-to-+4V window. The 
programming resolution is 10 mV. 

Tlie signals from the timing board to the output boards are 
fed to the rear p;mel There tlie signals are conthjcted out of 
the instnirrienl lluougli exchangeable semirigid cable bows. 
This makes it ijossibte to chai^ge the electiical length ^nid 
therefore the rlelay between the ou(t>ut rhcinrtels and the 
trigger outpul. Tiie advaiUage of deskewing the channels at 
this point in the signal path is that no additional cable that 
mighl distort the output jnilse is necessaiy at the outputs of 
tlie uistruuu^nL 

)Copr. 1949-1998 Hewlett-Packard Co. 

April IP93 He wletl-P^'kard JfmmaJ 6 1 

Signal In 

Variable DBby Kybrid 

Band Bond Bonii Bond Bond Bond Bond Bond dond Bond 

Bond ianil Bond Bond 47 nF 







cm 7 


Fig. 2. Schematic; diagraiii of Ihe variable delay hybrid. 


The delay block consists of an input shaper amplifier^ a %'ari- 
abie delay ibliowed by a second siiaper ajtiplifler, a switched 
delay, and an output shaper antplifier. 

Variable Delay. The variable delay circuit is a thick-film 
liybrid. Fig. 2 shows its schematic ciiagrara aiid Fig. 3 Ls a 
photograph of tlie hybrid. Diodes t "Rl to CRlfi are varacttir 
diodes. By changing their reverse voltage VyARDELt Llie ca- 
pacitance of each diode can be tuned between 0.6 pF and 2 J 
pF. The voltage Vvardel is programmable between -1,5V 
and -3GV, Fig, 4 show^s the delay shift versus the bias voltage 
at 50 MHz. To get higli resolution over the entire range a 1/x 
DAC is used. The bias voltage Vvahdel ^ equal to: 

VvARDEL - Vi + Va/PAC Value), 

where Vi mid Vg are constants. 

To achieve a variable delay without distorting the signal on 
the hybrid the capacitance of the diodes and the inductance 
of the bond wires must both be varied. Because the bond- 
wire inductance cannot be varied the signal is distorted and 
the delay Is a funclion of frequency. Therel'ore. a c aliV>rai if>n 
of the deiay as a function of the DAC value aiid frequency is 
necessary. Fig. 5 show^s the delay of the hybrid as a function 
of frequency before cahb ration and Fig. 6 shows the delay 
after calibration, \^^th the calibration, which nuis 100% auto- 
matically a delay accuracy of ±15 j3s is achieved over the 
full delay and freciuency ranges, hi (lie shaiuug amplifier that 
follows the vajlable delay hybrid the signal is j-efreshed 
(transition times better that 100 ps) and ampliJied to 2V pp. 

Switched Delay, The schematic diagram of the switched 
delay circ uit is .shown In Fig, 7, Fig. 8 shows the layout of 
th e sw i ic he d d e 1 ay I \ y b r i 1 1 . To ac h i eve I o w- loss i u i c rost rip 
lines, the hybrid is produced in thin-film teclmology, The 
different, delays are achieved hy switching between micro- 
strip lines of different lengths. Resistors Ri to R12 compen- 
sate for the on-resistance of the GaAs switches. Without 

these resistors the signal would be distorted by the reflec- 
tions caused by the on-resistance. The advantage of using 
GaAs switches instead of diodes is that no biasuig is neces- 
sary in the high-frequency path. The disadvantage is that 
tliese switches have a higher insertion loss, but this is not 
critical because the refresh amplifier following tlie switched 
delay hybrid has a higher gain (better than 20 dB) over the 
fuH frequenc^y range of the instnuuent thtui l he loss of the 
switched delay hybrid at maximum delay f typically 16 dB)* 
The nominal electrical lengtlts of tlie delay lines are: t^ - 222 
ps, ig = 401 ps, T3 = 748 ps, T4 = 1421 ps, 15 = 2727 ps. and x^ 
- 52()1 ps. In general: 

Tnu = L94Tj,-30ps. 

Thus, by adding a variable delay between I) and 222 ps to 
the switched delay, any delay between and 11 ns can be 
achieved with a resolution determined only by the vaiiable 
delay even if there Is a mismatch of ±3% ±15 ps between the 
different switched delay lines. Of the t otal 1 1-ns delay cajja- 
bility of iht* instrument, 10 ns is used to tlelay one channel of 
the instrument by ±5 ns wiOi respect to the othei^ chaimel, 
and 1 ns is used to deskew^ the two chiumels of the instrU' 
ment, that is, to compensate forihe mismatch in the 
transmission limes of the outijut i)oai'ds. 




Do + BWps 

Fig. 4. Dd^ of the variable delay hybrid a^ a amctimi af bias voltage. 

Fig. 3. \'ariablc deiay hybrid. 

62 April 1993 Hewlett-Packard .loumal 

)Copr. 1949-1998 Hewlett-Packard Co. 







Frei^iiencv (MHz) 


Fig, 5, Delaj* of the variable delay hybrid lis a function of DAC value 
and frt^quinicy before calibration. 

STtapmg Amplifier 

The shaping anipitfier is one of the key l)uildmg blocks of 
the instrument . The rliallenge of tlie design was lo develop a 
discreet e amplifier witli a fiequency range of 10 MHz to 3.5 
GHz, un (5i[tpnt amplitude of 0.2V to 2V pp (at^justablej^ and 
trajisition times better than 100 ps (GtVps t>i)ical 209Uo-80*Ki 
transition linies are achieved). The anipUiier was to be built 
only witii autoload surface mount components on a standard 
FR-4 HP pnnteci circuit board. 

The amplifier is a four-stage, ac coupled GaAs FET ampli- 
fier. The GaAs FET^ are mainly used in T\^ satellite receivers 
iijid therefore they are low-c*ost components available on 
reels Cor autoloading. Fig. 9 shows the schematic of one 
st<ige of the shaping ^implifier, LU determines the dc current 
Iket through HrJIRii. thai is, through Li, Li:^, and the FET Ql, 
Ijy coninvlliiig Ihe gate source voltage of Ql. Rvi is used to 
at^just the eurrent IpHT Al bigli fre(iuencies C.^HQi is a short 
cireiiil to ground mid the inducrors L|;4 and L[ have very 
higli ltn|>e(lmice. This nieaiis that llie hipnl of vkich stage is 
tenuinattMi in 50 nhrns within die freiiiieruy nmge of the 
ainj>[jner. Tlie resislur al (tie gate of the MJf prevents the 
amplifier from ringing or ostillatirig. Diodes C'Rl lo CE3 
protect tlie GaAs PKT fron^ damage when the t^ower is 

& I— 






Fig. 6. Delay of the variable delay hybrid as a function of DAC value 
and frequency after calibration. 

switched on or off. They also protect the FET if there is a 
nialfunclion in tlxe biiising circuit This is ver>' critical, be- 
cause exceeding die maximum ratings of the FET can cause 
a malfunction in the histrument weeks later, even after the 
bias circuit is repaired and the FET is biased properly. 

Frequency Measurement 

To make it jiossible to offer duty cycle, phase, and the same 
precision of delay and width in both the hitenial and exter- 
nal modes, a frequency measurement capabiUty is built into 
rhe instrument. The key specifications of the frequency 
measurement capability are: 
Accuracy: better than 0. 1% 
MeasLuement time: 300 ms 
Resolution: 100 kHz 
FVequency nmge: 2 MHz to S.3 GHz. 

Fig. 1 shows the freqtiency measurement circuits on the 
timing boairl that piepare the signal for the frequency 
counter, which is on the luit roproc*essor board. 

The itiain challenge for the frequently measurement was to 
get. a low -cost divider that works from 10 MHz up to 3 GHz. 
lAJW-eosi dividers lor telecom applit atioiLs operate only from 
10 MHz to 2.7 GHz, To solve tliis problem the trigger divider 

SwJiched Dcrtay Hybrid 





^z R3 











2 3 4 5 

Fig. 7, Hrhi'lii?sl.ii' duigrarn littlip swiirK+Hl drJjiv [lyhrid. 

12 t3 

April IBfiG Hewtetr-Pjirkard Journal 6.1 

)Copr. 1949-1998 Hewlett-Packard Co. 

Fig. 8. riiufogra[ili of \he. nmiclwd delay hybrid. 

is used. V^Ticn the instrument is m lining without di\iduig the 
trigger, the trigger cii\ider is by passe fi and progranmied to 
divide by 64. If the trigger is divided by 2, 4, 8, 16, 32, or 64 
the trigger signal goes through the trigger divider. Therefore, 
at the ou(put of the trigger divider the maxiniiim frequency 
is 1.5 QH'i (instrument rumiing at 3 GHz, triggei divided by 
2). This means that a low-cost, low-power frequency divider 
can be used after the trigger divider. 

The frequency measurement must work at frequencies down 
to 10 MHz at tlie external input, so the frequency counter' 
must work in a trequeney range from about 150 kH>s { 10 MHz 
divided by (^4) to 1.5 GHz (3 Gllz divided by 2), Therefore, 
the signal after the trigger divider j^oes through a static di- 
vider and is divided by 256. In a parallel path, a differential 
amplifier converts the signal to TTL levels. One output of 
the amplifier feeds a low-pass filter with a cutoff frequency 
of 15 MHic. A Schmitt trigger circuit detects the arupiitude of 
the niter output and tells the microprocessor whether the 
frequency is below^ or abovT 15 MHz. The nth;rot>rocessor 
uses the Schmitt trigger output to control switch 6. For fre- 
quencies below 15 MHz the signal g<jes 1 hr'ough rlie amplifier, 
byi:)assing the divide-by-256 dividerj while for frequencies 
above 15 MHz the signal is first divided by 256 atid then con- 
verted to TTL levels.^" Tlie resulting signal is divided by 16 in 
a standard TTL divitier and sent to the frequency coimtcr on 

' The byftass is necessary because the divide-bv-256 divider does n^t operate i)eluw ID MHi. 





n I — 

Bj R4 





CR3 CR2 CRt 





_L ^ 




To Nfixt Stage 
|50i2 LoadI 


Fig. a. ,Sc hematic- diagrani of one stage of the shaping amplifier. 

the microprocessor board, which Is an ASIC leveraged from 
tjie HP S153A lightwave itndtimeter. 

— ^oard 

The delayed output signal of the tiinhig board, a slngle^nded 
square wave, is the input, signal of the width boaid. Tlie 
width board generates the variable pulse width and contains 
the output anipUrier. 

Variable Pulse Width Generation 

As shown m the block diagram of the width board, Fig. 10, 
the mput signal is split into two signals. One of these signals 

Delay 1-^"^ 

Fig. 10, Biocli diagram of tht* width board. 

To Front 


64 April 19^3 Hewlett - Parkarf I .Joi \ nuil 

)Copr. 1949-1998 Hewlett-Packard Co. 

Input 1 

Input 2 


Nurfital/C i>inplein«nt 






Fig. 11. Block diagram of the 
pulse fttmiatter on ihe width 

is delayed by abcnil 4 as viitii a fixed delay line (semirigid 
cable). Tile other signal goes through a delay block thai ron- 
sists of two different hybrids — a variable delay hybrid 1 and a 
swiU heti delay hybrid — and two shaper antphflers. The t wrj 
hybrids ai>d the shaping amplifier are described earlier in 
this article* 

TltiiSt tw^o signals with the same frequency iire generated: 
one with a fixed tlelay of 4 ns and the other with a program- 
mable delay of 4 t\B to 14 ns (4 ns is the minimum delay of 
the delay block). In the puise mode, the delay of (he second 
signal is limited to a maxiimim of 4 ns plus the actual period 
value by Uie in.stxunient software. According to the instru- 
ment specification, this delay can only be programmed from 
4.15 ns to .3.85 ns phis the actual period value because the 
output pulse width is eqtial to this delay value ntinus the 
delay of the first signal ( w^hich is 4 ns, as mentioned above) 
and the specified minimum pulse width is 150 ps. 

PtiJse Formatter 

The two stiuare wave, single-ended signals are the input sig- 
t\als oft lie i-iulse fonnatter The pulse forniatfer Ls a custom 
bilRilar IC design*^d in HP's HPIX jjrocess. It is [packaged on 
a Utick-filni hybrid. 

The pulse formatter {Fig. llj is basically a high-speed EXOR 
(excIusive-DR) gate (EXl in Fig. 1 1 ). If cui EXOR gate gets two 
s<iuare wave signals of the ScUTie frequency that are delayed 
with respect to each other, it generates an output signal with 
a pulse width equiil to the delay between tin* two inimi sig- 
tuds liut with twi(x^ the frequeTK'y. Ilieivfore, the fnxjuency of 
the input signals is ilivided by two by tiie on-t:hi(} ilip-flop FL 

An addifional EXDR gate (EX2) enables the user to choose 
between normal motle and complement mode. The user can 
also switch the pulse fonnatter between the pulse mode and 
the stiuarc* wave inodc\ hi the square wave niorle. the input 
signal with t\w |>rogrammable delay is ciinnected to the out- 
put of I lie pulse formatter. Thus, the user can switch off the 
width capability of the instrument and have an additional 
(J-to-10-ns delay capability instead. This is especially valu- 
able in astiiiidartl inst.ninienh which dues not have the delay 
block on the timing board. 

If til e fretincncies of both input signals w^ere divided sepa- 
rately, using two flip-fiops, the pulse formatter could be 
either in the normal mode or in the complement mode after 
powering up the* instrtmien! or ch^mguig the frt^quency, 

delay, or width range. Tltis would depend on the inJdal state 
of the two flip-fiops and could not be controlled by tlie micro- 
processor This is why only one fli\1de-hy-tw^o flip-flop (Fl) 
is used here. The out|mt of F] is connected to the uvputs of 
flip-flops P2 and F3. wltich are clocked by the input signals. 
As a result, the pulse fomtatter always starts rmining in the 
norma] mode (self-initialization). 

The i>tilse fonnatter works froin ilc to 3.5 GHz and can (>ro- 
duf^e pulse widths as narrow as 120 ps or less. It has a differ- 
ential output with a swing of 500 m\' and transition times of 
about 80 ps (typical]. Tlie high level of the output signal is 
OV. The Input signals are ac coupled and must have a swing 
of 800 mV. The pulse formatter rcHiihres -5,1V antl +li)V 
supply voltages and dissipates 2,5W worst -case. Therefore, 
the Ijackside of the ihic k-filni hybrid is mounted on a heat 
sink made of solid ahiminuin. 

Output Amplifier 

The output amplifier is driven by the differential outputs of 
the pulse formatter IC. The amplifier consists of two identical 
(raAs K -s designed in HPs MMIC-B pnx-ess and fiackageti in 
a thick-film hybriiL 

The MMIC-B process is a depletion-mode MESFET process 
with a double-recessed^ (K35-|jni direct-wTite E-beani gate.^ 
It achieves an fj of 23 CiHz with a pinchuff of -L3\\ The ac- 
tive layer is grown with molecular beimi epitaxy and features 
a low-temperatuie buffer^ to eliuiinate backgating. *■'' 

Elach IC consists of two differential amphfier stages and one 
4.5V level shifter with a sotirce follower between them, as 
shown in Rg. 12. The layout nf the hybrid is shown in Fig. 
13, and Fig. 14 is a photrjgraph of the hybrid. The first IC 
drives the second IC thrciugh a level shifter, Tlte result is a 
four-stage dc-coutJled differentiaJ amplifier in whic^h stages 
on(^ juifl two are provided by the fii^t IC kind stages fliree 
and four are provided by the second IC. 

The GaAs ICs ret]Uire five vf>ltage and fotu- current sources 
each. These sources jtre lorated on the printt^d circuit hoard. 
Elastomeric contacts are used to connect tlie ptjwer supplies 
from die printed circuit board to the thick-film hybrid. 

Low-impedance bypassuig of the voltage supplies is essen- 
tial t<:» mitiimize overshoot and prevent oscillatif>n in tjie 
source followers of the anijilifler ICs. Byjiass is provided at 
low fret^nenries l)y surface mount capacitors on the pritited 

)Copr. 1949-1998 Hewlett-Packard Co. 

April VMi tiewli (( PiickardJimmal 65 



Test 2 

Test 1 Out 8 

Out A 



In A 




*SJ Is2 



Fig. 12. Schemalic diagrani of nn^ nutpur umplifier IC. a . pii^t differential amplirier with cascode. ^' Current, source Ijuffer. 
fcjUowers. rf Level sfiifLer. ^_ Second differential amplifier v\irh cascode. f Curreril source buffer. 


circuit board. High -frequency bypass is provided by 500-pF 
capacitors printed <:)n il\e hybrid iisini^ a paste that has a 
relative dielectric constant 6r= 1000. If surface mount ca- 
pacitors had been iLsefi on the liyLmd instead of the dielec- 
trie paste, the cajjacitoi"s wouid have been so large thai they 
cotUd not have been located close to the ICs. This would Itave 
increased bontl-wire inductances and caused problems with 
ringing and oscillation. 

EJastoineric contacts are a]so used to connect the input RF 
signal from the pulse formatten but are too relied ive at higii 
frequencies to be itsed for the output signal. Instead, SMA 
connectors are used. They are connecteci to the hybrid witji 
low-inductance ribbon bontls. 

Both GaAs ICs require a high level of about -1 IV at the RF 
inputs. Tile output signals of the pulse fomiatlerand the 
first amplifier IC have a high level of OV. Therefore, iw^o level 

shifts of IIV are required. Dc level shift is accomplished by 
an operatioiiiil amplifier circuit on the printed circuit board. 
The levels are sensed with resistors located directly on the 
HF strip lines so as not to add reflccti%T stubs. The high- 
frequency signal is parsed by lO-nf coupling capacitors in 
parallel witli the level shifting circuit. 

The 50-ohni temiination resistors at the outptits of both ICs 
are located extremely close to the ICs to avoid reflections 
from stubs. No reverse temiination is provideci at the mput 
of the second IC because IIV across the resistors would 
cause a very large powder dissipatioti. Becatise the reverse 
termination of the output of the first jimpLifier is so good, 
the effect of litis single reflection is minor. 

A good RF termination is essential at the input of tiie first 
IC. Because the bias at the input of the ^unplifier IC is -llV, 
simple termination results in a ver>' large power dissii>ation. 

66 April 1 9m I \e wlettPiu^kJircl Ji ) imml 

)Copr. 1949-1998 Hewlett-Packard Co. 


TnrifStllV FirttIC 

Level Shifter Voltafe Souiices 

Second ID 
To Second 11V Vsz Vqi Vjji Vsi V^^ 
L^vel Shifter 



u I t 1 1 













\ ^ 






'^^. I K 



A A 

n n' 






t:.\ til 


Tn F i rst 1 1 V Cu rre nt So urc es To Secon d 1 

Levet Shifter First! C Level Shifter In Isj hi 'si 

Second EC 

Fig, 13. Uj^'Miit of tfi^ output amplUier hybrtrl ICl arul IG2 are identk^aJ output lampliSer ICs. 

By providing a dc termination on the printjed circuit board 
(at a lower dr bias) and an at" termmation on the hybrid (a 
100-ohni resistor l)el^vt':eii I lie tRie and coniplentent inputs), 
a good RF termination is provided without excessive power 

Ferrites Ft5 and F4 (under the lid) and optional ferrires P5 
and P6 (outside the lid) reduce high-frequenr>^ ringing (at 
about 10 GH5!) on the RF outputs. Fl and P2 reduce reflee- 
tions bet ween the two ICs caused by the impedance niis- 
match of 1 lie output termination of the first ampiifier IC at 
about 10 GHz. 

The total power dissipation of both ICs is 4.5W worsL-case. 
To maintain low die temperattires, I lie backside of the 
thick-film hybrid is moimted oti a heat sink made of solid 
aliuninuiiL The heat sink is also used as a fixture foi^ die 
SMA connectors. 

The? high level of the f)utpul signal can be acljusted vtitli Vi^j^ 
(see Fig. 13) from -2V to +4V. For higli-lcvel values gieater 
than +1V, all voltage sources of the second IC are increased 
linearly witli Vmi^ 

The output amplitude is actjusted from OJV to 3,0V peak-to- 
peak with the currents 1*^1, Isi>, atui \^\ of the second ampU- 
fier IC (see Fig. 12). For amp!itiKles below^ hOV, I^j is 
switched off, and for atuplit titles below 0.33V, l^i and I52 are 
switch e<l tiff. The output devices aie scaled (i:2: 1 in width so 
that FET current densities are similar \\\ each range. 

The output amphtudc range is segmented to reduce over- 
shoot. An extensive calibration optimises transition time 
and ringing over the specified ainplihide, temperature, and 
fretfuency ranges. Tlie i>arait\eters adjusted in this opt.imi;5a- 
tdon are the operating current in the third stage of the four- 
stage differential arnpliller (Ii; Oi *h<^ ^^ig^ \^\'^\ of the third 
stage (\'i)2)i ^"^ Ihe cascode bias voltage of the fourth stage 

The output amplifier generates pulses with typical transition 
times of 50 to 60 ps (10'K> to 90%). The minimum pulse width 
specification is 150 ps, but pulses with a width of less than 
120 ps are possible. Overshoot and ringing are specified to 
be less than 15% + 20 mV; typical values are 5% to 10%, 

)Copr. 1949-1998 Hewlett-Packard Co. 

April 1903 Hfi wletl -Pac Vw r, I .If j 1 1 1 e u l] i\l 

Be Cti Probe 

Fig. 14. Photograph of Lhe oulput amplifier hybrid. 

Wafer Test of the Output Aiiipliiier 

The amplifier ICs are u^nted on- wafer usmg an HP 8 13 1 A 
pulse generator and aji MP ^12 IT tligitiKiiig oscilloscope. Tlic 
I( 's arc probed with a ( hin-fihn probe Ccoxi. Dc functional 
measurements and 2()^Krlo-8()% outjjut nse time nieasure- 
mentii are made al a number of output ampUtude settings. 

High-speed on-wafer testing is generally liniited to devices 
having a limited number' of RF sigitals and dc biases. Probe 
card technologies t>7>i<::iilly offer either excellent RF j>erfor- 
mancc at low^ <om])Iexity or high complexity and uiediocre 
RF perfoiTuance, Because of the fast transitu>n times that 
nuisl be verified in wafer test, the large number of dc con- 
nections, and die n^iuiremenl that power supplies be W' ell- 
terminated to c(jnirr.)l overshoot imci ringing in the output 
signal, no conunercially available probe technology was 
deemed capable of meeting our" needs. 

Spring- Loaded 
Center CDnductof 



I Line 

Center Hole 

Fig. IIJ. (Jross st:!f:ti(jiL of the prrjbr- f^fird showing Lhe probe niounlijig. 

The jjrobe card technology chosen is a custom thin-film 
probe caid^ in which short ( 1-inmJ Be-C'u probes are epoxy 
att^iched to 50-oluu inicroslrip lines in a hole in the center of 
a sapphire substrate. The substrate is mounted in a ma- 
cl lined nrefal frame intfj whicli nre mounted female SMA 
( oruiet inis. Ibe SMA connectors are spring-connected to 
coax -t.o-inicrost rip launclies on the substrate, allowing RF 
itnd dc coimection to each of theproiies. Aji exploded view 
of Ibe probe Ctird assembly is showii in Fig, 15, and detail of 
tlie probe att.achinent is shown in Fig. 16. 

Each dc source is connectetl to tlie proi^e card \da a bias tee 
as shown in Fig. 17. Ac temunation is supplied by connect- 
ing a 50'ohin load to the HF port of the bias tee. The probe 
inductarice. modeled as a single lumped element, is approxi- 
mately 0.7 nH. Thus, tiie RF tennlnation seen by the dc t>ad 
of the chip is approximately 50 olims m series with 0,7 nH. 

An alternate solution to provide byt:fassing woukl be to use 
surface mouul capacitors on the substrat*:^ lo bypass the 
power supiily lines to a ground provided by a plated via 
hole. This would tirovitie near ^^ero impedance at It jw fre- 
quencies, li^nfoilimately, the physical size of surface niomit 
capacitors would necessitate placing them some distance 
away from the probes and the short circuit woidd be rotated 
aroimd the Smith chart and W'ould actually appear open at 
al>oul 3 (Ah, Thus, the amplifier would tend to ring or even 

Because the sapphire substrate caimot be attached to a heat 
sink without mechimical interference with the wafer probing 
operation^ |>ower dissipation of resistors on the substrate is 
limited. Because shorted ICs or an erroneous test setup may 
force aibitrary abusive currents through the output load 
resistois, and a dajnaged tbin-fihn resistor woukl necessitate 
an expensive replacen'tejit, of I be substrate and probe assem- 
bly, we chose to provide the reverse temunation resistor for 
both outputs off the probe card. 

DC Pad 


DC Power Supply 


50U Microstrip 

Flg» 15 > Explotied view of tJie probe raid fnr wafer- testiiig the output 
amplifier ICs, 


AC Tennlnation 

Fi^. 1 7, lYobe cmd dv bias technique. 

6 H April 1 r+90 I Je wl€^tt-Pa<ct* ard Jo* i m al 

)Copr. 1949-1998 Hewlett-Packard Co. 

Oiitpm Pads 

i I soil Micfostrip 

^2 ^iMomA ^ soil Reverse 





O-^ tpoxy 

20-dB Pad 


Fi^, 18. Model of the probe csird 
ouiput Lrdnsmisslrjn lines showing 
reflections from disconiinulties. 

A model of the output probe cirrnil is shown in Fig. 18. The 
same circuil is used for both true and roinplement outputs 
of tlie IC. The IC does not contain its own reverse termina- 
tion resistor; its output is a switched current source and 
appears to be a higli impedance. The output requires a 
5l>-olun reverse tennination as well as a 5(>ohin customer 
loatl These loads ixr^ provided at the ends of two transmis- 
sion lines. The reverse termination is a replaceable 5(>ohm 
SMA load (HP 0960-0053); the customer loatl is an HP 
54 12 IT oscilloscope with a20-dB pad (HP 33M0C) for inptn 
protection. Each output pad has two probesi one for each 
transmi^ion line. 

Tlie pTObe card has two known discontinuities; a simple 
raj>acitive discfjntinuity at ilie coax-to-microstrif) trans jtjon 
and a more complex discuntinuily in the mvd of (lie probes 
juid probe-to-microstiip transition cojisisting of tapered 
liigli-impedance transmission lines for the probes aiKl a low- 
impedance hne in thearea of the epoxy. Reflections from 
tliese discontnuiities in the reverse termination ann cause a 
twoHlet) undei'Hltf>ol in the stej) resfwnse ils showii in Fig. 19. 
The longer underslioot is caused by Uie c(iax launch; Uie 
slioiter undershoot is c\iused by the etioxy mn\ t^robes. The 
lotal iunt>litude of I hese two midersboots is apjjroximately 
8% to IffMjof the input voltage step. 

Because a l(>M<^^-90%tnmsilion time measurement requires 
a repeatabie crossing of t tie 9(Bi^ iioiJit, small valuations in 
rin|*ing from die to die make a ItyMAo-llifya t ransititjn t ime 
measurement undependable, ReOections are far better 




24 SOOO n% 


Fig, 19, Trotie tard fuiljmi v\avi|(jrm showing uiidcrjshooiii caused 

by rrflt^ctians. 

controlled in tlie instrument application, but this probe 
teclinology allows us to make a 2^M-to-8(PAf transition time 
measurement that can be correlated Tsith the 10%4O'90% 
transition time in tlie instrmnent. 

High-speed puLse measiu-ements on-wafer allow the test to 
reject dice witli slow transition times or incomplete switch- 
ing problems before they are assembled into hybrids. Tl^is 
reduces rework and lowers manufacturing cost. 

All ac(justab!e signal par^cmieters of the Lnstiiuvient Cfre<:iuency, 
width, delay, amplitude, etc. ) are controlled by analog volt- 
ages generated by digital-lo-atmlog converters (DACs). The 
same is true for the voluiges tuuj currents ihat are responsible 
for signal ijerforniaJice in the an H)liner stages. 

The relationships between these control voltages aiid the 
corresponding signal [>arameters luv tjsually nonlinear and 
temperalure dependent. Tlic^y may lilso depeitd on other 
sigjial i^arameters (typiciilly fretiuencyj and vary from boaid 
to b(jaixL Tlie advantage of using DACs for generating these 
control voltages instead of varialHe jesislors is that the 
microprocessor can compensate for these influences. 

Ttie ideal solution would be to measure and store all fjaraiu- 
eter values at all possible DAC settings an<l letnperatures. hi 
practice tbis is impossitile because of the huge ajtiount of 
data and the time it wxjuld take to measure it 

hi the HP 8 133 A, all DAC settings are calibrated as functions 
t>f die corresjionding signal paiameters, tuid most of them 
are also calibrated as functions of frequency: 

DAC* = f(j>aratneter, frequency). 

To kee]> the amount of data manageable and the calibra- 
tion 1 ime and parameter setting time reasonable, a two- 
dimensional linear interpolation algorithm is used for all 

A linem* inten^oiat icm algorithm approximates the relation 
betwec^ti the incieiJt^nthnU value f prograjiinied signal i)a[am- 
eter) anti the dependent value (e.g., the 1>A(' value) with 
pieces of strmght lines. In the two-dimensional case there 
are a number of points of the firat independent, parameter 

April VMi th^wleU-Piix^katTi .Ivutnul 69 

)Copr. 1949-1998 Hewlett-Packard Co. 

(e.g. delay) and aiioUier number of points of tlie second 
iiidependeo! paniineler (e-g., freQueney) which fonn an 
array of parameter pairs. For each parameter pair a depen- 
dent valia^ is nieasiireti and stored. When the instninient is 
programmed to a certain p^irameter setting, I he dependent 
value is interpolated between tJie four atUacent parameter 

Eaeh relation between a signal parameter and the cone' 
spomiing DAC vahie is represented liy a t^alibration .strnc- 
fnre within tlie instrument. TliLs allows calibration of each 
parameter independently of the others. An example of a 
command to load data, into one of these structures is: 


This calibration command for tlie YIG oscillatoi^ defines 
ihree intenjolation points at 2, 3, imd 4 Gilz with DAC values 
of 888, 1969, and 3049, respectively. 

Altliough the R^M on the microprocessor board is batt ei-y 
buffered (and could therefore be used to store the cdibra- 
tion data) we flecjdefi to st ore tfie ciaia in an KKPROM on 
the corresj>onding liai'dware board ajKl loaci it into the rtiicro- 
processor RAM after power-on. We use 8K-byte BHt*K()Ms. 
The advantage of using EEPFiOMs is that the cidibralion 
data is seciu-e even when the batteiy is disconnected. It al^o 
makes the instiTunent more easily semceal:»le, t>ecause re- 
placenunit boards can t>e calibrated in the factory. The only 
tiling that has to be recalibrated after ijoard exchange is the 
delay skew between the tw^o output boards. 

Temperature Cvali brat ion 

As mentioned above, most parameters have a temperature 
dependent variation. For most paiameters the temperature 
deperidency can be described with adequate precision as a 
linear function of the temijerature difTerence between tlic 
eunent temperature and ttie temperature at calibration time 
(AT). For ot.lier parameters llie temperattire dependency is a 
linear function of AT times the current interpolation vahie. 

To compensate for these two kinds of temperature flepeu- 
dencies. we store an absolute timJ a relative leniperaturc 
coefficient together with tl\e anit>ient temperature at calibra- 
tion time with each calibration structure. The ambient tem- 
perature in the instnunent is measured with a temperature 
sensor on the timing board. 

Wlien the instrument is progivimnied to a certain parameter 
setting, the result of the inteipolation is mofiitled using 1i\e 
following formula: 

\^ue„pw = Valucoid + ValuCoidTCrei AT + TC^bs AT 

w here Vahie(^jjij is the parameter value as calculated with the 
iiiteri)olation, TCVpi and TC^bs ^ic the relative and absoIiUe 
temperature coefficients storetj witfi the c^dibration structure, 
and AT is the difference lietweer^ the current temperature 
and tiie temperature at calibration time. 

Using tJiis method reduces the delay drift, for example, from 
150 ps to typically 20 i)S over the operating temperatime 

lechanical Design 

The EMC (electromagnetjc compatibility} desigi^ of tlte 
HP 81.33A pulse generator Ls a combination of mechanical 
design and electrical design. Since 1092, the RH standard 
for HP products has included the new Europe^ui standard 
EN5501 1 (ClSPRl 1 J class B limit (similar to the LIS, FCC 
class R UmitJ. Tlie product had to meet tliis new standard. 


The HP 8 1)^3 A Pulse Generator is built in an HP System 11+ 
cabinet witli a height of 123.6 umi imd a depth of 497.8 mm. 
In this mainframe a rnair^ eiiassis is mounted to carr>' tlie 
power supply and above it the microprocessor board (see 
Fig, 20). The cai'dcage is built nuo the chassis, and the tim- 
ing board and one or two output boards are installed in the 

At the hegimiing of the project w^e planned to leverage the 
mechanicaJ design from the maijiframe of die HP 8130x4 and 
8131A pulse generators. 1 lowever, during the first imple- 
mentation of the HP 8i;J3A hardw^ire m the IIP 8130/V31A 
mainframe, w^e found that the radiation was over the limits. 
What were the reasons for the greater emissions? The HP 
S130A/31A mainframe was designed for a 5()0"MHz maxi- 
numi frequency aiifi 200-ps transit ioji ttmes. The HP Sl'i:3A 
has a 3-GH/. maximum frequency arul < lUO-ps transition 
times. This meajis tliat the HP 8133A generates more power 
at high frequencies tlian the HP S130A and 8131 A, especially 
above 500 MHz. 

Measurements showed that the main sources of radiation 
are the timmg board, tlie ouitnu t)oards, mid the cat>les to 
the rear piuiei and the tront pmieL For sufficient shielding 
we had to improve the design of the mainframe. 

Output Bi^ard 2 iCh^mfi^Z) 

Qut|iirt Board 1 {Chaimel 1} 

liming Board | 

Power f 


Fig* 20* Main assemblies of the HP 8133A pulse generator 

70 April 1 mn 1 Jewlet i-Patkarri Joi i nial 

)Copr. 1949-1998 Hewlett-Packard Co. 


The cardcage with the liming board and the one or two 
output boards inside is a sheet-metal assembly. We made 
the follomng mipro% ements to increase the shielding (see 
Fig. 21): 

' Reduce the diameter of the perforation holes. We found that 
a hole dianieter of 2.4 mm is acceptable. We also found that 
an expensive honeycontb filler panel for the fan area is not 
neressai>' when using a 2.4-mjTi-diame£er perforation |>atteiii. 
Reduce the holes in the comers of the eardcage to the 
smallest ijossible size. These holes are necessaiy for pro- 
duction of tlie sheet-metal t>arts whenever two ortiu-ee 
bentLs form a comer of a part. 

Reduce the distance bettveen screws or rivets, A distance of 
about 25 nmi is acceptable for good shielding in the HP 
8133A frequency range. If the distance between the screws 
or ri^-ets is greaier than 25 mm, use contact springs to close 
the seams. 

Avoid seams where ever possible. If there are any seams, 
they must be closed w iih contact springs. 
Close all renuiining lioles that are necessary for manufactur- 
ing the paits of the eardcage assembly with contact springs 
or additional parts. 

Use semirigid cal>les for iJte high-ir^quency intercomiections 
to the front and rear panels. For this purpose the eardcage 
is extended to the front panel wi^iere the SMA. comiectors 
are located. Tiie eardcage is also extended to the rear panel 
in the iirea of the S^L\ coimectois. Here we ukc a milled 

Rear Panel 


SNIA CannectDrs 

A Rear Supparl 



Pow e r S up p I y Q nd Timing B oar d a nd irtptjl B oaiid(st 

Mlcrojirficesiior Board 

filler CDnntclof MQiheiiifiarri 


\i . \ 


at Cardcage 

Fig. 21. '\'n\i vii'w t)f tlie Mr'^Hi;J:iA niMinlrcKiir'- 




SMA tlonnector 

part called the rear supp<m to mount the SMA comiectors 
^id semirigid rabies. 

New Ideas 

The mtprovemenis listed above were not sufficient to reach 

the RFl limits. Therefore, additional ideas w ere needed. 

We di%ided the motherboard into two parts. One part is 
mounled in the eardcage assembly and makes the CPl" and 
power interconnections betw^een the timing board and the 
otitput iKiartis. The second part of the niotherboard is located 
on the out^side of the eardcage assembly and is connected to 
the CPU board and the power suppiy. 

Between the tw^o parts of the motherboard is a filter coimec- 
tor wjtli "34 pins, mounled with i!s housing inside of the card- 
c^e assembly. The feedthrongh pias of the filler connector 
are plugged on one side into tiie ronnector of the internal 
niotherboard iind on tlie odier side into the extemai mother- 
boaiTl The ft iters are pi inters consisting of two capacitors 
and an inducior. The result is a high insertion loss for high- 
fre<|iietu\v eneig^v. 

Tlie filter connector mast have a low impedance at high fre- 
qitencies t<i the ground of the eardcage. The filters are sol- 
dered into a niter plate and die filter plate is screwed to the 
Side of the eardcage to provide the required low* impedance. 

We also looked at riltered D-subituniature connectors instead 
of the filter connectors, but these D-t>pes are too big for our 

Because of the capacittve load of the fiiter connectors, IGs 
of the ACT nmiily are needed as flevice bus drivers on all 
the prinleti cit^cuit boards m the caidcage and on the 
tnicroprocessor board. 

No additional Rri strips or RFI gaskets an^ necessaiy in the 
cabinet. No additional measures were necessarj^ to avoid RF 
emissions in the design of the keyboard, microprocessor 
board, or power supply. 

EMC Summary 

After many meiLsurenipnts qjkI niodific atiotts we were able 
to meet the RFl stamfimis, Tlie llT Hi:i:iA pulse generator 
has piissed the ClSPRll Class B reguULtion. The measure- 
ments required by the EN 5501 1 rt^gnlation will be done us- 
ing production instruments. Tliis regulation allows a transi- 
1i{)n period until mid-l99'i to flo the nieasuiements. Tlie 
EMC (iesigii als<j helped rneel Ike EN5(H)82-1 standard, 
which prescnhes immunity to electrostatic dischaige (l^SD), 
radiation, and fast transients. 


'Hie anllu>rs would like to thank Dale Pittock. Mark Mathews. 
.Jiju Taylor, and .lohii Tiiiloch. who helped design and develop 
tests for the v^uiable delay hyluid, the pulse foniialter hyhiid, 
m\i\ the outiJiit amplifier hybrid. Tliey also thaiik Bill Mmphy, 
who develo[>efl the pulst^ hm nailer IC, Jolm Doinrjkos, vvho 
sup[>ort.ed the design <jf the variable delay hyhridj arul Bob 
Fisher^ who worked on the wafer test for the output ampli- 
fier K'. Fiuiilly. the authors wish X<:\ thank Jochen Weimer, 
Ralf Meltsch, and Benitl for t lieii' work on the 

A| >ril I W^ 1 1(^ wlott -V\kv Icartl Jt HimiiJ 7 1 

)Copr. 1949-1998 Hewlett-Packard Co. 

printed circuit board layouts, Heiko Stemgraeher, Krnst 
Bauer, and Martin Schweizer, who made it possible to mount 
the surface mount parLs of the shaper amplifier so close 
together, Werner Konimayer, who pro\1ded a lot of informa- 
tion about the print t^d circuit board process, and tlie people 
of the metaj shop in Boblingen. 


L EJl. Wong, B- Kf*jif]olf*r. B YoatSj N, Fernandez, and D. D'Avmv2o, 
"A Sell- Aligned l>oiible Hecessed, Sub-Half Mic.Tf.jn Gate Process for 
MMJCs Using Dl'V or E-Beam lithography," presr'titifi al fhe TitU- 
tcen ih Sia Ui-of- [he -A H Prog rum o ft Cvmpou i i d Sa u i vo n dtietn rn 
(SOTAPOCSXHi), Elerlrochemica! Sorlelij Meetimj, October 1990. 

2. L,G. Stndebaker, "EitH^troTi-beani written multilevel resist process 
applied to GaAs 1^'ETgate fabrication," SPIE Elevtron-Bemn, X-Ray, 
and Ion-Beam Technology: Subtnicronu'fer Li thoffrnpkieii Vfl, Vol. 
1089, 1989, pp. 112423, 

3. N,G. Fernandez, M.J. Liglimei, D, DAvLiii^o. G. l^atteraon, and J.E. 
Turner, '^Growth, Processing and Reliabllily of Low Teinperature 

Bulfers for Higli Perfomiance MMlCs,** Pi'oceedfngs of the Ttveifih 
StafeoJ-tiw-Arf Pwgium on Cornpound St^mirondurtotTit (SOTA- 
POCSXII), EleHrovhemiml Society MeeVbig, May 1090, pp. 

4. C. Kocot and C.A. Stolte, "BackgaLing in (iaAs MESFETs," IEEE 
Trurmuiiims on Elf^rfron DevU'p^, Vol ED'29, July 1982, pp. 

5. C.P Lee, S.J. Lee, aiid B.M. Wc>)ch, "('airier liyection and Backgat- 
ir^g Effecl in GaAs MESFETs", iEEE Ehrhott Devlvt^ LHU-rs, WA. 
EDU3, no. 4, Aph] 1982, pp. 97 98. 

6. SXJ. Klein aiid FI.J. Wagner, "AoOO-MlU Pulse Gei\eraior f)utpu( 
Sectlou,^ HetLielt-Pafkiird Jouimalf Vol. 41^ no* 4, August 1990, pp. 

T. A. Aniistrong and HJ. Wagner, "A 5-V P-P 100-ps GaAs PuLse Aiu- 
fjlifier K' with Improved Pulse Fidelily." IEEE Jonrmd ofSofid- 
Slale Chrtilts^ Vol SG-27, iio. 10, October \m2. 
H. DP f lombnt kli\ R.L. Van Tnyl, V. Potcrson, cind R A, Fisher, "^A 
Microw^avf^ Probe Systemr HewipttPavkard RF and Afkrowave 
Mm*^urwnent Sympfimum^ 1980. 

72 .April {9m Hewten-Rirkard JoiimaJ 

)Copr. 1949-1998 Hewlett-Packard Co. 

A Multirate Bank of Digital Bandpass 
Filters for Acoustic Applications 

Real-time frequency analyzers have been used for over twenty years for 
acoustic noise measurements. Recent advances in digital signal 
processing technology have improved the performance and usefulness of 
these analyzers. The HP 3563A portable real-time frequency analyzer, for 
example, makes complex acoustical measurements easier and more 
affordable than ever before. 

by James W< Waite 

An acoustics t^st laboratory will typically have a variety of 
test equipment for the characlerization of product noise. 
Fimdamental to the n\easuren\ent of noise emissions is a 
l/3Hictave-baiid frequency analyze^ but sound level meters 
and FFT (fast Fourier tTaiisfonn) analyzers may also be 
present and useful Digital signal processiitg (DSP) has for 
some time allowed custom digital hardware to he used in 
the design of both octave -biiscd rccm^ive-lllter analyzers 
and iastrumenls relying on the FFT. It has only been recently 
however, thai DSP cliip Lechuologj^ has advanced to the 
point where it is possible to implement a variety of acoustic 
measurement algorithms on a single hardware plal form aiKl 
run at the required reaJ-tinie rales. This paper discusses the 
(icvelopment of these DSP algorithms and their itn{)le menta- 
tion in a small f3.2-kg) battery-operated instnjment, the HP 
3569A porlahle real-time frequency miaiyzer (Fig. I J, 

Octave -Band versus Narrowband Analysis 

When measurement .s of acouslit* sound pressure level are 
presented as a fund it in of frequeucy, d logarithmir fonnat is 
normally chosen. At^ousticians prefer la see ihe ilata dislrib- 
uied in constant percentage bajidwidllis, usually octave or 
l/Il"Octave bands, since the auditory perc^eption of somid is 
logarithmically related to freqiLency and several regulations 
require such presentation. 

Many modem sped nun anal>"^ers otJerating in the standard 
20-Hz-to-20'kHz fretnu-ncy range use the fast Fourier trans- 
form for quickly translating time-domajn signals Uy the fre- 
quency domain spect.nun. This approach is widely accepted 
and offers sonic^ unique capabilities for evaluating cross- 
chjinru^l system behavior in the frequency-doniahi data by 
means of coherence ^utd frequency response fund ions. 
However; the FFT has a severe liniitatitHi for use in acous- 
tics. The output of d\e FFT has a constmit b^md width dis- 
tribution rather than a constant percentage hamlwidlh dis- 
tribution, til at is, the frequency sc*ale is linear rather than 
logaritfimic. Wlien 1/3-octave frequency bands ^ire synthe- 
sized by perlbrminj^ a weighted sum of hnear-resolutioji FFf 
bins, the frequency of the lowest band is limited hy a lack of 
resolution at the low-frcquenc y end of the spcctnnn. 

A typical FFT spectrum aj>alyzer has HOC) lines of resolution. 
For a measurement span of 20 kUz, this ?l!1ows a spec tral 

bin spacing of 25 Hz. Since acoustic* measurement standards 
require at least 5 to 10 FFT bins to svTithesize a single 1/3- 
octave b^md correctly, the lowest l/;3H3ctave band that can 
be accurately synthesized using this data is 500 Hz, five oc- 
taves higher than desired. Workarounds for this problem 
have their own limitations. One possibility is to iLse a much 
longer FFT, say 16,384 l>ius, to provifje nuicli I welter U>w- 
frequency resolution, ami another js to do niuiti pie-span 
FFT^, effectively generating a log-resolution output. 

These and other approaches that start with the FFT, how- 
ever accurate in output, must still address the issue of real- 
time performance. Acoustic signals me hy tlieir ver^' nature 
nonstationaiy in time, so an FFT analyzer thai claims to 
match the performance of a traditional bank of analog 

Fig. 1, The UV [ibmh\ rf^al-iime freciuency analyzer aiul the HP 
352^1DA sound intensity jiroba 

April !nSJ;UIewl**tr-Parkiirf|jQumal 73 

)Copr. 1949-1998 Hewlett-Packard Co. 

I/3-octa\T bandpass filters must ovpriap data arquisition 
iuid pro€*essing, and ran not disregard samples at its iuiaJog- 
lo-digital converter at any tinie. Even in tins world of ever 
faster prore:^sing horsepowf r, this is a difficult task given 
the considerations listed above. 

Filter analyzers are not without tlieir own shortcomings. 
( .onslajit percentage barKhiiidths allow only coarse fre- 
quency resolution tow^ard die higher end of Ihe acoustic 
spectnuUj making the measurement of discrete tones diffi- 
cult. Many computer and disk-clrivc mannra«'t iirers musi 
locale irritating hi j|h- frequency noises emanating from tlieir 
products. Tlie baiidwkltii of the 16-kHz 1/3-octave band is 
nearly 4 kH^, making a precise spectral estimate of the tone 
imp<issible. Also, at k)w frequencies, the ver\' narrowband 
1/3-octave filters have long impulse responses, resulting in 
lengthy filter settling times. The potential for zooming in on 
a narrower frequency range using a local oscillator is not 
realistic for filter analyzers, although this feature is widely 
available in FFT analyzers. 

Wavelet Analysis 

One promising technology that bridges the gap between 
coustani [>;jndv\ itiUi FFT aniilysis and crrnstant percentage 
baj 1 f I w i < 1 1 i t real - 1 i i n e km aly si s is t a 1 1 e 1 1 1 lie i h eo ry o^ wave- 
lets. Wavelets have properties that make them very attxac- 
five for the measm'ement of sound. Wavelet transfonns aUow 
a logarithmic frequency axis (i.e.. good frequency resolution 
at low frequencies), and have arbitrarily good time resolu- 
tion at hij^er frequencies, imlike the block-oriented FFT.^ 
They have much more fiexible bandwidths than filter analyz- 
ers, histnimentation intpl emerging discrete wavelet trans- 
forms has yet hj ai>peaj\ and faces signiOcanl obstacles in 
supplant ing 1/3-octave analyze!^ because of the regulat t>ry 
natiue of acoustic noise measurements. Practical application 
of wavelets is begimiing to appeal' in the acoustic trade jour- 
nals ,- but for the imniediate futiue, the world of sound is 
seen thrtnigh the poles ami zeros of bimdpass filters, analog 
or digital 

DSP in Acoustic Measurements 

Digital signal processing has not. byt);LSsed the acoustics 
conununity. Digital filters have for some lime replaced the 
old analog 1/3-octave filter bankSj and are available as ciedl- 
cated real-time frequency analyzers or tilter analyzers, as 
distinguished from FFT spectrum analyzers, dynamic signal 
analyzers, and others that derive their residts from the FPF. 
The digital filter analyzers are typically composed of a subset 
of single-pirr[Jose filter gate arrays, bit-slice microprocessors, 
and medium-scale integration DSP multiplier-accumulators. 
Such dedicated har<iware hiis tnatle it difficult for the digital 
filter analyzers to perform otliei sigruil processing tasks 
such as, for instance^ the FFT. Acousticians do use tiie FPF 
for certain measmements, especiEdiy cross-channel analyses 
and tone detenuination, so any analyzer that could mtegiate 
digital filter aiuilysis in i/;3'OCtave bands with the FFT would 
Imve a c!istii;ct advantage in the marketplace. 

In 1991 llewlett-Packaid introduced an PFT analyzer, the HP 
yD665A» thai also perfoims tnie digital 1/3-0 ctave analysis 
using the comt>i nation of a 20-MHz Motorola 5G0CI1 DSP chip 
and a digital filter gate array. Tiie gate aiTay perfonus band- 
limiting low-pass niteruig m an all-pass, multiple-sample-rate 
mode. The same gate array serves as a bandwidth limiter iii 

the FFT measurement mode, so the DSP measurement hard- 
ware is shared between the measurement tasks of the instru- 
ment. This configiuation, tbntigh jnt.egi'aling two tradition- 
ally separate* instnuuents into a single btjx, still relies on a 
very costly development^ the filter gate array, because there 
is not enough powder in the 56001 to perform all of the tasks 
required tor real-time digital filter aiialysis to 20 kHz. 

Just one yeai' later, the clock speed of the Motorola 56000 
f>eries pnjcessor doubled to 40 MHzj remo\ing any remain- 
ing tjarrier to the software inipiementation of a combined 
FFf and real-time l/^^-octave analyzer on a chip. This goal 
was realized with the int.roducrion of the liP 3569 A, which 
incoq>orates the combined functioncility of a dual-channel 
FFT imalyzer and a real-time i/3-of tave sound intensity fil- 
ter analyzer, in addition to an integrating sound level meter 
and a reverberation time processor. The wholly digital pro- 
cessing allow^s very higli precision, unknovvn to date in a 
handheld package. 

In the following sections, we will explore how the standard 
1 /3-octa ve fi 1 1 e r s I \ ap es aje im pi e men t ed as d i g i t al fi I le rs , 
starting firs! with a ntmierical <iesign metliodology, mid con- 
tinuing ItJ the actual software arciutectme. Tiien we will 
examirie some of the design elements, unique to the digital 
domain, that make possible ver>^ accurate real-time cross- 
chamiel calculations of acoustic mtensity jmd full-bandwidth 
correction of microphone phase mismatch m sound intensity 

Signal Processing Block Diagram 

A description of a 1/3-octave filter analyzer using an off-the 
shelf DSP cliip is primarily concerned with a software algo- 
rithm, but we will first present a general pictme of the HP 
3569A measurement harchvare. Fig, 2 is a block diagram. Al! 
mea.sureme[its take place in the Motorola 56002 DSP ciiip, 
while the Intel SO 186 proc essor is responsible for display 
processing, management of the nonvolatile RAM disk, and 
the user interface. For any stand-alone instrument, the user 
interface finnwme is a significant aspect of tlte product de- 
velopment effort. In this paper, however, we are concenied 
with a description of the HP 3569A measuremem algorithms 
aiKl signal processuig. We shall show tliat the entiie measuie- 
ment of acoustic pressme or twoH:"hamiel acoustic intensity, 
mcluduig triggering, averagmg, scaling, and coordinate trans- 
formation To dBSPL (somid pressin-e level) is performed by 
the 5G002 DSP chip. Data output is over the 56002 host inter- 
ftice, w^hich m our case had a D>L\ chtumel detli cated to it for 
fast result storage. Because of the modularity of the system 
with respect t,o the measiu-ement algorithms, a DSP archi- 
tecture similar to Fig. 2 citn be useci as the measurement 
engine for any instniment or computer-based user interface. 

We designed the system to include two independent channels, 
since cross-chaiuiel ai^alysis (e.g., frequency response, cor- 
relation) is one of the benefits of FFT analysis, and since it 
makes possible tlie measmement of real-time sound intensity 
in 1/3-octave bands. 

Sound Intensity 

Sound intensity is defined as the rate of sound energ>' trails- 
mission per miit area, and represents a vector quantity that 
has many uses to noise control engineers. F'or example, 
mtensity can be used to estimate I he sound power emitted 

74 April 1 9&S He wlett-Pac kar d Jaumal 

)Copr. 1949-1998 Hewlett-Packard Co. 


Mitmphone i1 


^"P*rt AMiAriasing 

Circuit Filter 

Mrcrajihone tfl 




Digital I/O 

Fig. 2. 1-Jfirdwarp blo^ik diagram of the HP '35rj9A real-litne freqiieMcy analyzer. 

from a device or the sourui absorbed by a panels or to map 
I he sound fteld in a noisy aireniJt cabin. 

The primary attractiveness of offering intensity measure- 
ments in a portable analv^er is that it allows accurate in-situ 
nteasuremenls. Single-chamiel pressure measurements re- 
quire assumptions about the en\1ronment — for example, 
that the sound tlekl is either anechoic or re^erberaiive. 
Since this is hkely not the case for most industrial environ- 
ments, a noisy de\1ce under test must fretiuently be nioved 
into a special chamber for acoustic evaluation. Using inten- 
sity measuremeiits. a two-microphone probe fPig. 3) can 
discriuiLTiale between background noise and a directional 
sound source, facilitating accuracy without severe 
environmental const rainls. 

Mathematically, intensity can be expressed as the time aver- 
age of pressiu'e times velocity. Euler's equation relates veloc- 
ity to the lime rate of change of pressure at a microphone/* 
The resulting expression for the mean sound intetLsity takes 
the form: 

where p] is the soimd pressime at microphone 1, p2 is the 
sound pressure at microphone 2, Ar Ls the distance between 
the tuicrophones, and p is the air density, 



^ — *^ — ^iHHfll 

Fig. 3 depicts how signals from tw^o pressure microphones 
are combiiied to compute intensity in 1/3-octave bands. For 
this time-domain calculation of intensity to have sufficient 
accuracy, the microphones as well as the measurement 
channels must be veiy closely nuilched in iihase ((102 de- 
grees below 25(1 H'A according to IfX' 1043, a statulard for 
intensity measuring iastniments). There *ire also d>iiamic 
range requirements placed on the processing system, in that 
the pressure difference between the two channels can be 
very small while the pressure magnitude can be large, rcsidt- 
ing in pretusicm eiTors for fixetl-poiiU microprocessors. We 
chose to imi>le[nent lt\e fligilal intej^rator using the traiiezoid 
rule, whit^h has a desired 9n-degree phase shift at jUI fre- 
quencies less than the Nyquist rate. The outpm of tlie soujtd 
intensity caJculation Ls lime averaged, converted to dB, and 
sent to the htjst processor. The frequency range of interest 
for sound intensity is 20 Hi lo 10 kHz, which results in 28 
bands of intensity inl'ormation calculated in real-time. 

Sound Pressure 

In the more camnion singJe-channt^l or dual-channel pres- 
sure measurement where inletisity is of no concenu the out- 
put of each l/!Voctavr niier is magnitude squared ;md rime 
averaged over a user-entered integration time. Since tlie 
1^3-octave digitid filters run it^ real time and provide an out- 
put for every saniple inptit, int:egration times can be very 
short> limited only by the speed of the DSP chip. Realistic 

Press lira IntensJtv 



Fig, 3. Procf^ssin^ nif^ihod tn 
ctHiipnti^ ^[iiint] intrhHity, 

April 1993 Itowtptt Pfirkard Mmmal 75 

)Copr. 1949-1998 Hewlett-Packard Co. 

mlninuim integration tinii's are on the order of a few niilli- 
secnndts, Lndependeni of frequency. Only the impulse re- 
sjmnse of tlie bandpass filter limits tlie practicality of using 
ver>^ short average times to monitor transient events. We 
again contrast this to ihe FFl] which reqiijre.s a lime record 
length propoitional to the number oflines of resolution. 
Normally this is on the order of 20 to 30 n^illiseeonds at ttie 
2tl-kllz acoustic frequency sijan, E\'en willi overlapping of 
the input tune records, lite FFV tends to smear out transient 
events botli in time and frequency. 

Not shown in Fig. 3 are optional processinj? steps subsequent 
to the calculation of pressure and intensity. For example, a 
maximum or minimum hold feature can hold the highest or 
lowest output of the averager within each l/.'W>ctave t^and 
over some specified time. Minimum hold is usebil for uTea- 
suring backgromid noise levels measured in a room that 
may be impacted by temporary noise events^ like a ringing 
telephone. For each l/i^-nctave filter, an ampUttide histogram 
is maintained havuig resolution in dBSPL. Thus statistics are 
available as a t>ostprocessing operation on the histograms. 
One common statistic is caller! the exceediiiice ievef defined 
as the percentage of tinie thai a particular ]/i>octave band 
sound level exceeded a proscribed dBSPL value. 

Sample Rate Declination 

One w^ay to ftesign a b;uik ol' digital bandpass filters that 
simulates the traditionrxl analog l/;3-octave Otter sets is to 
derive a unique set (jf 11 Iter coefficients foi eacii desired 
center frequency. These filters would all run at the sample 
rate of the analog-to-digital converter (ADC), resulting in 
?mge demands in processing, particularly when the number 
of desired frequency bands is large, histead, the HP SfifirJA 
uses a nuiltirale system, as shown in Fig. J. By progressively 
lo wen Jig t.lie sample rate of the system after ciich set of tiiree 
bandpass 11 Iters, we reduce the ainoimt of work needed to 

process the entire bank of filters. Accordit^g to the Nyqiiist 
sampling theorem, we require a sample rate for each octave 
only a factor of about 3.3 above the center frertuency of tlie 
highest l/3H">ctave filter within each sei of three filters. For 
every ADC- sample input to the higliest stage, the average 
work turns out to be equivalent to six bandpass filters plus 
two decimating low^-pass filters (or twice the work required 
to process the highest octave's filters), as depicted by the 
discrete processing blocks in Fig. 4. 

Another imporliint atlvajitage of 1 he decimation approach to 
the digitiU filter bimk is tliat each set of three bandptiss fil- 
ters, centered at 1/3-octaves within each octave of process- 
ing, is independent of sample rate, such that the pole-zero 
positions of the filters ui the z ]jlane are identical for all oc- 
taves. This is a result of the relationsliip between the sample 
rates and llie center frequencies of the fdters. As im illustra- 
tion, the l/3H3ctave center frequency of 20 kHz divided by 
the sample rate of the highest octave, t^5,53(> Hz, is (irecisely 
the same i\s the center frequency of the 10 kflz band divided 
by its sampte rate of 32,768 Hz. Thus these filters have iden- 
tical fomuilations in the z-dommn, and only tiiree distinct 
bandpass filters need be designed for the entire 1/3-octave 
filter bajfk. Similarly, the decimating low-pass filters aU have 
the same pole-zero topolog>^. 

This is a nontri\ial advantage over any analog filter bank, in 
which each bandpass filter must be indi\idually designed for 
tlatness and shape- However, a small problem arises because 
traditionally accepted center frequencies have followed the 
base- 10 system, f = ItJ-^'^^'^", wliere <n <45. The digital 
method follows a base-2 fornuda, f = 1000(2^"-^^^'''^), For n = 
43 (20,000 Hz), 1his results \n a center-hand frequeticy error 
of about 1 percent. Although the difference is small, both of 
the m^or 1/3-octave filter standaids in existence (ANSI 
SI. 11-1986 and lEC 25&^199X-Draft.)4'^^ allow either method 



4096 Hz 

8192 Hz 

tW f^ 

Input from 

16394 Hz 


BIfiB ffi^s! 


▼ w 

Am &00 630 

800 1000 t2S0 

1600 2000 2500 

i 1 i 

3150 4000 5000 

6300 8000 1D0QO 

■*Br H- 

128 Hz 

250 Hi 

512 Hz 


1024 Hz 

2S 31.5 40 50 63 80 100 125 160 ZOO 250 115 

Fig, 4. Tiie digital 1/3-ootave filter l>a]ik tor one channet The numbers under the filters are the center frequencies of the 1/3-octave fillers. 

76 Ap ri 11 mn T^e wl ptt -Pat kanl ,f oi i ntal 

)Copr. 1949-1998 Hewlett-Packard Co. 

and require that a filter set be marked as either base^lO or 


Phase Aeciiracy 

Another advai^tage of tlie ciigital method relates to cross- 
channel phase accurare Refening to Fig, 3, we see that the 
calculaTion of intensity occurs after the bandpass filters, so 
that the intensitv' output represents a \'alue band4iniited 
mit^iin n particulaf lA^ octa\x\ Since digital filters have siatile 
arid decemiinistic transfer fimctions. we can be assuretl that 
no relative phase difference between chaimels Is uttroduced 
Ln the filtering process. For ihe digital 1/5-octave analj^er, 
only Ihe iuialog anti-aliasing filters and the ac-coupling ca- 
pacitors, botli of w^hich precede analog-to-digital conversion, 
can significantly affect cross-channel phase accuracy. In 
contrast, it may not be possible to design aji accurate ^malog 
lyS-octave intensity analyzer because of the required phase 
match between the bandpass filters. Keeping such systems 
calibrated and matched would be ari arduous task. 

Finally, the all -digital processing ciHow^s a pliase compensa- 
tion technique for which there is no equal iu the analog pro- 
cessor Fig. 4 shows a phase compensator [ilaced v^ltliin the 
prcK^essi ng chain at the H)24'Hs! satt^ple rate, such that the 
phase of all downstreaJtt (Calculations is ac^justed to the sec- 
ond ciiaimel as a function of frequency Note that Fig. 4 
shows only one channel of a tw^o-chajinel sound intensity 
processor. The compensator is a unity-gain digital filter with 
adaptive coefficients to correct for pliasc mismatch bctw^ccn 
tlie individual microphones of a sound intensity probe, irt 

Depending on the accuracy required, additional phase com- 
pensators can he placed at any sample rate in the signal flow 
grapli. A nniltiorder digital compensation network can tailor 
tii*:^ jjhase'Verstis-frequency characteristic by cascading the 
effect,s of several low -order compensators. The multiple- 
sampl€*-rate topology used is especially well-suit ed to this, 
since a phase anomaly that may only atTect very low fre- 
quencies need only be corrected at tliose frequencies. 

Filter Design 

Five types of filtering are performed in the HP 3569A digital 
1/3-octave analyzer, cili n|ierathig in real-time siintiltaneously: 

• Low^-pass filtering and flecimation l>etween sample rates for 
each octave 

• Either sixth-order l/3-o('tave or fonrti^enlh-ordtT octave 
digital Bultenvorlb l>aiidt)ass filters 

• Discrete integration using a simple flR (infinite impulse 
response) filter (tJte trapezoid rule) 

• A single-pole low-pass smoothing filter to allows exponential 
smoothing of the detected filter output 

• Varialile^coefficient IIR phase compensation filtei^. 

Digital low-pass filter design is well-known and we called 
upon a Pf design tool called Dispro* (manufactured by 
Bignix, Inc.) to detemunc the coefficients of an eighth-order 
(8 poles, B zeros) elliptic low-pass filter. This digital anti- 
iiliasing filter has Dfl-dB rejeclion ai a rnHjuency oT i)M^ mv] 
less than O.0f}3-<1B passhiuid rippltv Ihc pas.stnind edge begins 
at0.2fi5, aiulat the ciecitnated Nytiuist frettu<*n(y or().:d5fs, tlie 
attenuation is 30 dB. Afier dist^ardirtg eveiy i>ther san^ile, 
the new Nyquist frequency is decreased by a fiictor of two, 
Aliijsiilg is not a concern since the l> filler afh^mnition 


/ X I \ \ 







g -3n 




S jai 




\n \ 




^\ \ 




y ^ 

\ \ 

5 6 7 S 9 1{l 
Frequency (kHz I 


Fig* 5. l/'i-ort^vp filter stiapes used in the HP 3569A real-tinie fre- 
quency analj^er Tlie plot shows the effect of the digital decintating 
loW'pass filter. The luw-pass lilter has an inpu! .sample rate t if fi^,5i36 
Hz. After low- pass filtering, everv' other saniple is discarded and the 
new sample rale is 32,768 Bk. This is uspd as the baridpass filter 
sample rate. Thus tlie Nyqtiist frequency is 16,;184 Hz. 

is significant in the frequency raoge (1.25fs to O.^Ofg. The 
combined effect of iow-pass tmd bandpass filter stopband 
rejection at the new Nyquist frequency is oyer 80 dB, as 
shown by Fig, 5. 

Poljtope Optimkation 

For tiie bandpass filter design ^ a different methodology was 
used. We used a bnite-force nuniericaJ method called poly- 
tope optinilzation to find the best position for the poles of 
the filters. Standard filter design programs (like Dispro) do 
not aliow^ trails it ion bcUvds to be specified on a constant per- 
centage bandwidi li basis. In die pol^l^ope method, each of 
the six pole po.siilons is compared wiQi the nominal ANSI 
third-t:)rder ButterwcHth filter shape, resulting in a niininiiza- 
tion prcjbleni in six variables (the pole positions). The poly- 
Intje fttelbo<l, described by Wright/ assumes notlting al>oiit 
the continuity of the function. It compares the eiTor {\w I lie 
least-squares sense) of the transfer fiuiction resulting from 
the current placement of the six poles to the tiirgei filter 
whajje. Each pok^ is positioneci at the center of a. small 
triiUTgle inside the unit r-irr le on Ihe z plane. T\\'o vertices of 
the triangle are lield constant on eacli iteration. A new pole 
position is evaluated by fiipping die triangle on one of its 
sides, so that the new pole position is at the center of the 
Hipped triangle. Veitices are stretched according to the mag- 
nitvide of the error Eventually the j)ole positions converge 
to the best location for the biiiidi>ciss filter. Severe penalties 
are levied by the design program if poles are placed outside 
of the unit circle, for tnslance. Excessive passband ripple is 
liandled in the same way All the zeros of the system lie on 
the real axis al either dc or the Nyquist frequency, and thus 
are independent of tlie filter's center frequency. The positions 
of the zeros iire pretlethied and ai e incorporated mto the tar- 
get equation- Fig, r> j^hows the magnitude response of ;ill three 
l/;5-octavc bandpass filters over tlie 80-dB operating range of 
the system. The topology of the filter is shown in Fig. 6,2 

The polytope error fiuiction failed to provide the necessary 
nam ess in the passband for the fourteenth-order octave fil- 
ter (one filler per octave). Since only one filler iiad to be 
designed mid r^eplirabHl across all txtavcs, astandaitl ana- 
log Btitierw^orUi filter was designed iutd IrmLslornied to tiie z 

April inftl Ht^wlott I'rK karf! Irmmal 77 

)Copr. 1949-1998 Hewlett-Packard Co. 

domain iismg thc^ bilinear transformation. Excellent pass- 
band ripple pei-forniantx' was obtained by thijs approach. 

for in the processing, particularly for fixed-point DSP chips, 
where bit growlli and overflows are a concern. 

Flow Graph Optimization 

The positions of the 1/J-octave filter zeros follow from the 
analogue to ButterwTjrth bandpass filters. We want to hmit 
the power transmitted through the filter close to the Nyqiiist 
frequency, and hence place a zero there (z = -1). The filter 
also mnst attenuate low fretjuencieSj and Iberefore we place 
another zero at dc (z = +1). Tiirough evaluation of tlie final 
error function as output by the polytope design method, we 
fmd that increasing the number of zeros at dc reduces the 
ripple in the passband of the filter hi fact, we place three 
Keros at dc. resulting in a very convenient direct-form FIR 
(finite impulse response) filter for the zeros. By cascading 
zeros, we find in the z domain: 

(l-z)(l-z){l-z)(l-hz) = (l-z)Cl-z)(l-z^), 

which is iniplemented as a cascade of three simple FIR filters 
having unity coefficients. 

Passband rippie is one ingredient hi tJie accuracy grade of aJi 
ANSI 1/3-octave filter. The filters shown in Fig. 5 have less 
than ±0.008 dB ripple, and when this is combined with the 
dechnathig low^-pass filter ripple of ±0.003 dB. die worst-case 
passband ripple is 0.022 peak-to-vaUey. This is equivalent to 
a Tyv^ i ANSI SI. 11 fdter or Class lEC 225 filter 

A small compb cation arises in that the three bandpass filters 
have different gain factors. Syntliesis of the filters shows 
gains on the order of 100 to 200, which must be accounted 

Discrete Integration 

The integrahoji filter used in the sound Intensity measure- 
ment is implemented as a simple IIR digital filter. In the cal- 
culation of intensity, il is very important that the integrator 
impart a precise 90-degree phase shifi to the sample data 
stream. This is accomphshed by use of any symmetric inte- 
gral fimction, for exan^ple the trapezoid rule: 

yfnj = y(n-l) + (l/2)[u(n) h- u(n-l)]. 

Simpson's rule also has good phase performance and better 
amplitude accuracy over all frequencies.^ However, in the 
presence of high-frequency noise, the trapezoid rule excels 
since it attenuates signals close to the Nyquist frequency 
instead of accentuating them as does Simpson's rule. As is 
evident from the impulse response y(n), the coefficient mag- 
nitudes are cither 1.0 or 0.5, so the filter can be implemented 
by adds and shills. i\l though the Motorola 56002 can multi- 
piy as fast as it can shift by one, not having to maintain 
pointers to multiple coefficient tal>les is a significiuit advan- 
tage. Fig. 7 shows the magnitude response of the digital inte- 
gration filter. Although not shown, the phase characteristic 
is precisely -90'~' from dc to the Nyquist frequency. The mag- 
nitude of the fdter response is a fmiction of frequency. To 
compensate for the rlifference between the trapezotcUrule 
magnitude and the itieal, a gahi conection is applied to the 
center-band ft'equencies of the ITS-octavc intensity spectrum. 




^ l_ 

-J I- 





Channel 1 
Pole Output 

Channel 2 
Pole Output 


Pres^uf e Scaling 


K Average 


Intensity Scslrng 


X Altera ga 


Fig. 6- Flow graph of the band- 
pass filler zeros and poles, single- 

7H A|>ril l9^t:U!i^wlellPatkEirdJounia! 

)Copr. 1949-1998 Hewlett-Packard Co. 
















Log Freqaeitcy 

Fig. 7- M3^1ud{^ characteristic cif l\m trapeaoid integration filter, 
^jhowing canformaiice to the ^-dB-ppr-ocl-ave roli-oflof a iheoreli- 
cal inte^TitiorL fimciLion. The pimse chiiracteristic is precise!^' -90° to 
the Nyquist frequency of 16,3S4 H^. 

DSP Software 

TJie most central aspect of the processing represented by 
Fig. 3 is that sotne logic must control wiien ttie filters of 
each selected octane lu'e nm. Tins is hatidleft by a ^'pass" 
look-ut> table- At every new santple frotii Oie MJC, an ele- 
ment is reati from Llie table, which has a modulo length of 
2^"^ where N L^ the number of octaves. Tlie value retmiied 
front the look-up taJ^le is the number of octaves to process 
before retiiniing to read another ADC sample. The first few 
elenients of the table are: 

In the Uinit, the average niunber of passes perft>rrned on each 
ADC sample is two. One itei'atton of a "while*' loop executes 
all the processing encompas^sed by ihe discrete blocks shown 
in Fig. 4 for both input chajinels. as well as detection and 
averaging of the output. Hg. 8 shows C-langtiage pseudocode 
for the bigb- level corttrol flow. F'or performance reasons, the 
iicl ual inij>lemetnation is iu 56002 assem]>ly language. 

Fixed-Point Scaling 

Scaling of the fixed-point l/3-ociiive analyzer caktilations is 
a significant implementation issue. With the ntultiple filters, 
sample rates, and gains enibtxlitnl in ll\e prtKessi tig system, 

while ( AOC FIFO nut empty } 


Real] ADC sample from FIFO lar Chl&l 
Peteci overload or Iriggier CDndition 
took up ciirrent pass counr from table 

while \ pasa.cownt- -I 


for ( each of three 1/3-i»cia¥e fi Iters f 

Ch1 bandpass filler 

Dh2 bandpass filler 

Do intensity cefcutation 

Accumulate results 
Perform low-pess decimation fifter 


Iff ADC sample module 64} 

Ceovert accumitlalers le black fleat 
Perterm exponential and linear ai^eraging 


Fig* 8- Pseutlg-codc lur the oct^ivf pr^x-essing loop. 

one might be tempted to suffer a higher part cost and em- 
brace floating-point DSP chips for this application. Actually 
the choice is not so ob\ious. The floating-point chips re- 
move the possibility^ of overflow and underflow results from 
the signal processing, a m^or advantage. However, the 
clock rates and multiply-accumulate times are not signifi- 
cantly differeiti. Both the Motorola 56002 and the ilotorola 
96OO0 run at 40 MHz. Tlie power consumption of the fixed- 
poini chip is much lower and the price differential between 
the ctiips is a factor of four. 

We chose to take on the Increased software burden and 
solve the multitude of scaling issues that arise in the fixed- 
pomt case, because of the attendant benefits. The sc^Ming 
considerations are many. Since we have a multipie^sample- 
rate system, the accitmulation of pow^er m the detection and 
averaging section varies greatly across octa\'es. The band- 
pass filters have % erj^ large gains. Progranmiable integration 
times cai^ range from miUiseeonds to hours. One way to 
limit the percentage of processing time tised in detecting 
and managing arithtnetic overflows is to design the software 
so that scaling is done at deterministic inteni tits, rather titan 
testing for overflow s on every miUtiply-accumulate operation. 

Tliis deterministic stealing bas Ijeen built uUo the pass look-up 
table. One of die highern^rder bits of the pass count is en- 
cod eti with a flag to force a nomtalizalion of the output data 
every 64 ADC samples (approximately 1 ms ai a sample rate 
of 65,536 tiz). This amortizes the overhead of scahng over a 
much longer time than if the built-in 56002 extension bits 
w ere put to use. AlsOj since the rate of bit growUi per octave 
is retluced by one-balf for each low^er octave, the same pass 
count table ean h>e itsed to determine the ntimber of octaves 
to normalize on each 64-point bomtdary. This is aceom- 
[jlisbed by a second pointer into the table that increments 
only once per 64 points. Thus, after tite Rrsi millisecond, 
only the higliest threes 1/3-octave baiuls {U\, tbe Iiighest- 
sajnt>lt^-^^h? processing block in Fig. 0) itre tu>rmalized, since 
they iiie tlie only ones with the full 64 accumulated filler 
outputs. Tliis approach minimises the amomtt of work done 
to mountain ftdl 244nl precision fixed-point calculations. We 
estimate that less tlum two percejit of the available CPLI 
cycles are used in the detemtinistic scaling algorithms. 

Normalisation as implement t^t in the 560f)2 1/3-octave ana- 
lyzer forms a 48-bit fractional mantissa mid a 24-bit power- 
of-two exponent for each l/3-(>rl;i\c [land output. Until the 
64-point boimdary is reached, only llu^ act^umulatof otitputs 
(without exponent] of the averaging process are saved be- 
tween ADC* sami>les. Bach successive t>4-poinl nonnaliza- 
don hitervfil comt>iues the latest acc^umulator output \x\\h 
the current floaling-point sum (inclufling exponent). 

Scaling of data before output includes acljtistments for linear 
averaging time, aggregate gain (through all filters and inte- 
grators), and unet|ual accuniulatifm between octaves. These 
operations are (>erformed as [>seuclt>floalJng-pOitit opera- 
tions in tbat they may operate oti the exponent, ihe man- 
tissa, or both. Maintaining an exponeiU with tbe data is espe- 
cially convenient because tbe end lesiill nfall the scaling is 
a conversion to base- 10 logarilluTis. This arnotints to a 
base-2 log table look-up (using the mantissa as the index), 
which when added to the existing exponent gives the full 
basie-2 iogarhlun. Asuuple multiply Qien convert.slo base Ml 

April I m\ I Ii wlctt-PsK kard Joiinui] 70 

)Copr. 1949-1998 Hewlett-Packard Co. 

s: 100 


n,-rr| n 


\ \ -— H 

Ti rrh 

11 r—i n 

r • - \- \ \ \ -\ — — \ 






§00 KHKI 20O0 4000 8000 1B0Q0 A L 

Frequency {Hz) 

S; IDOj 





Time (s| 


Fig, 9. (Lop) IIP 3569 A 1/3^ 
octave display wilh A -weighted 
aiid linear levels, (bottom) Slice 
display from XhB HP 356 9 A sliow- 
jn^ thp time history of the A- 
weighted sound press iirf level 

In sofh^^are, a circulai' FIFO is maiiitaiiied by aii ADC iiiter- 
nipl routine so that the main filtering loop is allowed to fall 
tpniporarily behind the data converter. This allows for 
longer processing delays resulting from data iiomialization, 
conversion of acciinmlated pressiu-e and intensity to dB, and 
data outpiib Although it occurs infrequently, it can take up 
to 1/2 miilisecoTui to take the log of both the pressnre and 
hitensity spectra (all Ki5"0c!:ave band.s). For tiiis puiiJose, a 
FIFO length of at least 32 samples per rhaJ^nel is re(|uired. 
In reality^, a large 512-sample FIFO Is used to ajlow^ asyn- 
chronous command processing from the SOlSfi controller. 
Some of these conmiands {e.g., clearing the current average 
accumulators and mnplitude histognuns) utm take several 

Overall Sound Level Bands 

'IVaditional A-weiglited sound measurements have been ac- 
<|uired using simple sound level meters. Most octave-based 
analyzers have eased coniparison of tlie octave data lo dBA 
by providing an oveiall level at The right.-lmnd side of the 
octave data (Fig. 9). The HP 3569A has two overall bands 
that can simultaneously show both the A-weighted and lin- 
ear overall levels. When a mai'ker is positioned on the A- 
band, the readout is precisely what would be measured us- 
ing a sound level meter. The calculation is performed in the 
DSP as a simple weighted block multiply of the Unear- 
weighted l/3<jctave bands, unless the analog A-weiglit filter 
is already switched into the signal path. 

Optionally, tiie liivear band can be replaced by an overall 
impulse measurement, another function f omid in sound 
level meters for measurement of impulsive noise, TMs is a 
special 35-niillisecond exponential lime weighting applied lo 
the broadband time data after frequency weighting by t he 
analog A-weight filter The measurement is perfonned at the 
maximum sample rate of the analyzer (65,536 Hz in one- 
chtmnel mode) m parallel witii 1/3-octave analysis. Fig, 10 is 

a graphical oveiview <jf the sound level meter capability of 
the HP 3569A. 


'IViggering and overload detection are handled by the 5fiO02 
internipt routine. Wlien these events occurs a status word 
associated with the current ADC sample is tagged with the 
appropriate event and placed into the input FIFO. Later, as 
the filtering loop reads the ADC sample out of the FIFO, 
actions are taken on the events. Triggering ui a real-time 
filter analyzer does not initiate data coliection^ since the 
I/3-octave and low-|>ass dec i mat ion filters all must be run- 
ning and settled when the trigger occms. hi stead, the status 
of the latched trigger line is polled on each new sample. Tliis 
allows special trigger modes not normally associated with 
FFT spectnmi tmalyzers. For example, gated averaging 
specifies that the output of the bandpass filters be linearly 
averageil wliile a 'fTL extern td trigger is asserted. The lime 
resolution ft^r this gate can be as little &s 1 ms, nuiktng pos- 
sible triggered tnmsient event analysis in KKjctave bands. 


Filtered pressure mid intensity outputs can i>e averaged by 
either linear or exponential methods. ^Tten exponential 
averaging is selected, the filter outputs are smoothed by 
miother simple digital filter: 

y(n) = {l-A)y(n-l) + Au(n), 

where u(n) is the current filter output and y(n) is the current 
average output. The constant A is related lo a time constant 
of the exponential rate of change of the analyzers output in 
response to an instantajieoiis change at the input. Standard 
time constants used by acoirsticians are 178 second (fast) and 
1 second (slow). The factor A can be expressed as A = tA, 
where t is the decimated sampling interv^al mtd t is tlie de- 
sired time constant. In normal cases A is Quite small for the 

80 Ajjrii 1995 Hewlett Pac If ard Journal 

)Copr. 1949-1998 Hewlett-Packard Co. 




Time Constairl 
Slow; 1 s 
F»5t 125 ms 





Fig. 10, Liirear and exponential averaguig are done on tlie squared output of eatti l/3H:ictavp frequency band, ilii* output of the averager is 
( (jnvMrlPfi to dBSPL ( sound pressure* If' vol). 

higiier-froqiiency 1/3-octave bands and increases for the lower 
bands. A special case of exponential averaging is called equal 
confidence averaging, whklt varies? Uie lime constant for 
each 1/3-oclave band so as u> disinbuie llie variance equally 
across the spectrum. In this case, A is constant for all bands. 

linear averaging is simply a uniformly weighted time average 
of the accmniilate(i pf>wer passed by a pailii'ular l/'3-ociave 
filter over a predefinetl intenal. If the measurement is set to 
repeat, tiien the acrumulator outputs Jire set to zero and the 
intensity integration filler is reset withoul mtssbig any new 
data S£imples. Fig- 1(J depitis how line*ir fuid exponential av- 
eraging are impleniented in the context of a digital real-time 
f r eqi i e n cy an aly ze r. 

One of the primary advantages of real-time frequency analyz- 
ets is the ability to ouijiui repelitive spectra at very short 
intervals. The I iP ;J5i)JlA collec^ts each averaged spectrum (at 
interv^als as short as 4 niillisecoutts) into a iuultis|)ectrun^ 
buffer A view of a Lime slice ihrougb this buffer is presenteil 
on the lower display of Fig. 9. A shce of spectral values is 
available for each 1^^-octave frequency b^ind, enal>ling iire- 
cise examination of the components of any transient event 


Tire design i)hilosophy of a digital 1/3-octave Olteril^ilyzer, 
as implemented on a single fixed-poinl DSP chip, has been 
presented. The main goal of lliis develoiuiient is to allow 
general -purpose signal analysis using both FFT and digital 
filter niethocfs without hardware dedicated to either pur- 
pose. This fiexible approach has many advantages, espe- 
cially as it pertains to real-time ptiase correction of sound 
intensity pre jbes. 

A ckn o w 1 edgm e n ts 

Many thanks to Chiis Sutton, who was the hardware designer 
for the [IP 3d69A. Early product b mi n storms with C'lms 
showed that the hardware used for FPT analysis was ne^irly 
identical to what was needed for acoustics applications and 
1/3-octave analysis. Withoin the skiU of PMI llollenhorst, IIP 
3569A project rtuitiager. to generate enthusiasm for entering 
a new market area, the descril)ed deveiopmerUs would have 
never taken place. Randy SaHin, Neei Malik, Mike Ilall^ Eric 
Tilman» Rick Van Ness, and Dave Dintenfass all made key 
contributions during the course of the project* 


1. U. Hiout aiul M. Vi*tterii, *"Wawlel^ and Signal PrrKi^^sliigt" U^EH 
Signal I^oces^tug Magazine, October UW^l, pp. bUlH. 

2. RV. Bruel, "" Practical Use ofAeoxi^Xic Te^huologj' for Measure- 
nientii i>f Flufrgy Flow, Holography, iuul Wavelets." Pmeefdings of 
NoiseCoH,. July Vm^pp. 11^28. 

;i. G. Kasmijssen. "Intensity — lis Measurement and Uses,*' Sotind 

mifl Vilminon, October iJJSfl. pp. 12-21. 

4* Americmi National Stamiani: S^ie^ification/vr Ovtave-Bnmi 

and Fmxrtional-OciatJe-Band Analog ami DigUat Fillers^ ANSI 

SJ.lh!9H(y, Standards Secreiariat, Af oustii iil Sf^^iely of Atnerifat 

New York. 

5. ItitrritniiOiifil Kloi'trote^iudcal Commission Drajl SltiHdairi, IFC 

104-J-!9lL\\ ith^trifmentfifor the Measiirmnent of Sound httf^nHitg, 

199] Uraft. 

II J.W Waite. '*l"mie- Domain t'onipensation far MiLTf>phone l*hase 

Mismatch/ Proceedings of Intcmoise-92, Toronto, pp. HST-lltKi. 

7. HE. (rill, W. Murray, and M,H. Wright, Practical Optimization, 
Aradrmir Prrsfi, 1981, pp. 94 9fi. 

8. i^W, Haniuung, Dtglfoi Fiitfi'i^, Second Edison, Prentice Hail, 
1977, pp. m^i. 

April 1 903 Hewlett-Packard Joun i ;lI 8 1 

)Copr. 1949-1998 Hewlett-Packard Co. 

Continuous Monitoring of Remote 
Networks: The RMON MIB 

An introdLfction to the capabilities of the Remote Monitoring Management 
Informatfon Base of the Simple Network Management Protocol and its 
implementation in the HP LanProbe II network monitor. 

by Matthew J. Burdick 

Over the past several years, staiidards and open systems 
tiave become important in tlie computer indiistrj^. Inter- 
changeable elements in customers' computing systems offer 
a number of benefits: no de|>enflence on a single veudor, flie 
ability to compare similar products from nniitiple vendors, 
Luid the safety of aji assured future upgratie path, Jn nef wuik 
management, no standard has more successfully ridden the 
crest, of the st^mdards wave than the Sunple Network Man- 
agement Protocol (SMMP)."^' Nowhere have the limits of the 
SNMP protocol been explored more fully than m the Remote 
Monitonng Management Information Base (RMON MIB}.^ 

As networks Ixave grown from isolated islands supporting 
small groups to pcr\'asivc and critical components bi the 
operation of large organizations^ the need to monitor these 
networks at all times has become increasingly important. 
When networks were small, iJOrtabie protocol analyzers 
were sufficient to ensure continuous operation. When prob- 
lems developed, an analyzer could be carried to the network 
in question and troubleshooting could be performed. As net- 
works grew, how^ever^ it became more difficult to transport 
analyzers to trouble spots. Certainly it was impractical to tie 
ii|> the analyzers to perform routine network monitoring in 
an effort to provide proactive network troubleshooting. Dis- 
tributed network monitoi^ or probes till this role, providing 
historical trend data, lists of network users, and coriUnuous 
monitoring of netw^ork activity. 

These probes are physically similar to network routers — they 
contahi a network Interface or interfaces and prt>\ide no user 
interface. The RMON probes continuously coUecl r^etwork 
data, which can be gathered from the prrjbes by a separate 
mtmagement station via the SNMP API (application program 
interface)- Because all the probes can he managed fron^ a 
single management station, they are low-cost management 

The capabilities of an RMON probe will be discussed after 
ti\e fol I o wi n g b ac kgro un d into rmat ion. 

RMON History 

In 19SS, the Internet Activities Board (lAB) released RR' 
1052t lAB RecomiJiendations for the Deveiopfueni ofhiternei 
Network Management Standards. ^ In it, (he older Shupie 
Gateway Management Protocol (SCJMP) was generalized and 
renamed SNMP The name change reflected the evolutionary 

' UnfortufTatqly, ttia use of scranyms Is ubiquJEQus throughoui The Intemei ^^ndartls process. 
Please refer to the Gbsssry at right to tlacbde untainiliar terms. 

changes applied to the gateway management protocol to 
traiisfonn it iitto a general network management protocol 


Quoted iteiTis are frDrn dacument RFC 131 D, The Internet Standards Pwcess, af the 
Internet Activities Board. 

Agent: A prabe, device, or prQCKss that cnllects data and makes, it available via 
SNMP in the form Df an MIB. 

API: Application pragram rnierface, a well-defined functional interface between a 
software application and a SBrvice. 

CMIP: The Commryn Management Interface ProtocoL a complex OSl network 
rnanagEment protocol. Pronounced "see-mi p." 

Gateway: A node that joins two networks. 

lAB: "The Internet Activities Board (lAB) is the primary eoordinatirig committee for 

Internet design, engmeering. and management." 

IETF: "The JAB has delegated lo its Irnernei Enginaering Task Fofce (IETF) the 
prinnary responsibility for the development and review of potential Internet Stan- 
dards frrjm alJ sourrres, The IETF fonns Working Groups 1o pursue specific techni- 
cal issues, frequently resulting in the development of one or mare specifications 
that are proposed for adoption as Internet Standards," 

JetDirect MIB: An MIB defining the HP LaserJet printer's interface to the network. 

LanProbe: HP's remote monitoring probe. SIM MP and proprietary versions are 

MIB: Management Informetion Base, a tree-shaped hierarchkiaE database 
containing objects. Pronounced "mib," 

pert View: HP's umbrella network management system. 

RMON: Remote Monitoring Monitoring a network using a management station 
physscalJy separated from a series of distnboted pmbes. Pronounced "ARE-mon." 

RFC: A request for comments issued by the lAB Each flFC describes a protocol 
used on ttie Internet. 

Router: A gateway that performs network-layer routing. 

SGMP: The Simple Gateway Management Protocol, the precursor of SNMP 

SNMP: The Simple fretwork Management Protocol, an evolutronary development 
of SGMR 

SMI: Structure of Management Information, the definitions of object types' in an 
MIB Described in RFC 1155. 

Sun Net Manager Sun Microsystems' umbrella network management system. 

S2 Aprii 1&93 llewlett-Pairkard Journal 

)Copr. 1949-1998 Hewlett-Packard Co. 

Natutmlly» in view of th^ gateway roots of SNMP, the first 

iniplemenlati ans of SNMP occurred in gateways such as 
hubs aiifi routers. These devices offered a set of network 
statistics known as a Maimgement Information Base (MIB). 
Later* other devices offered expanded sets of slattslics, each 
referred to as an ^UB. The ongin;iJ MIB. MlB-l, was ohso- 
leled and replaced by MIB-II. In ad«fition, each vendor of- 
fered a dilTerent set of data knov^Ti as a priv-aie. or enterprise- 
specific, MIB. Each of these MlBs is registered, or released 
to the public, at weil-publiciz«i archive sites on the iniemel. 
At the time of this writing, enien>rise-specific MIBs from 12 
different vendois have been registered * 

One 5U<"h NUB was registered for tiie Novell LANtem network 
monitor. It provided some of the advanced netw ork manage- 
ment features included in liie UP LanProbe;' but access to 
the probe was available via SNMP Tliis valuable feature 
allowed network majiagenient applicatioi^ such as HP 
OpenView and Sun Net Manager access to the probe's data. 

The RMON MIB builds on features in the HP L^iProbe, 
Novell LANtem, and other remote network monitors. It was 
developed jointly by a ^roup of people from a variety of ven- 
dors, inckiding HP. Its gotd is to st^mdardize tiie data presen- 
tation and control of these dissituilar network moniiors. 
Today, there are more than 10 anrtoiinred implenu^nlaiioas 
of die RMON MIB, atuf supfjorl eontinoes to grow. TItis ar- 
ticle win famyiarize the reader with rlie capabilities of the 
EMON MIB and its Implementation m the HP l^nProbe E. 

SNMP Oven lew 

Althougli a thorough overview of SNMP would be quite 
lengthy, some understanding of the basic ideas is necessaiy 
to undeistand the RMON MIB. Before describing Uie RMON 

' For acjiess tp the rsgnslBfed enterprrse-specific MJBs, ftp afiofiYiTiciusly to tiast vanefa.isi edu 
and reUieve files from Uie mib directOfv 

MIB^ the reader must grasp the organization of data in the 
SNMP tree, the typ€?s of objects contained in the tree, and 
operations available to manipulate those objects. 

The foundation of SN^IP is a tree-structured data base com- 
posed of subtrees railed MIBs (Management Infomiation 
Etases). Each MIB is intendetf to contain infomiation spe- 
cific to various network devices such as rouiens, bridges, 
remote monitors, and perhaps even printers and other de- 
\1ces not devoted solely to network activity. For instance, 
MIB-I Lmd MIB-II allow monitoring and control of general 
network devices, while die enterprise-specific MIB for the 
Jet Direct card (an netv^'ork expansion card used in some HP 
printers and plotters) provides information relevant to tiie 
status of the printer. 

Fig. 1 shows a subset of the SNMP tree. The fiill tree is not 
maintMned at a single site. It consists of a number of MIBs. 
each of which nmy change independently of the otheis. This 
is particularly true of MIBs local efi mider the Enterprises 
branch, since each MIB here may be maintained by a 
separate company. 

Although the tree in Fig. 1 shows only one end or leaf node 
(gd Statu sPaper Jam), each such node represents an SNMP 
objecl, and is named by listing the path from the root of the 
tree to the object in question. Objects that are not columns 
in a lal>le have an additional suffix of appended. For exam- 
ple, the gdStatLisPaperJam vfiriabie in the JetDirecl MIB indi- 
cates the current status (jf the printer — a value of I htdicates 
a paper jam while a indicates no jam. Its object ID is 
I A6.L4.L11.2.:J.a 1.1,2,9.0. The trailing zero is there be^ 
cause gdStatusPaperJam is not located in a table, A manage- 
ment stijlion such as HP (3penView must query the printer's 
agent for llie value of this object ID to detennine the status 
of the printer. 

ISO Org DQO Internet 
1 3 B 1 




Interfaces {2\ 

At 13! 

if (4) 


TCP 16} 

OOP (7) 



Transmissien flO) 


Generic IF (Ul 


Statistics 11} 
Hfslurv {2} 
Alarm (3) 
Hosts {4f 
Matrix (0) 
Filter 17) 
Capture [8f 
Event (9) 

gtistalusPaperJam (9} 
gd Status Entry [2\ 

generalOeviceStaliis (1 1 

Private Enterprises 
4 1 


iiet_printef ttl 

nm System \Z] 

2 Interlace [4f 

SNMP (13) 

Pig. i. A fHirlinr^ of the SNMP 

)Copr. 1949-1998 Hewlett-Packard Co. 

Apiil \m:^ McwU4t-Parkiin1 Jonmiil HH 

12 12 12 

A B C D E F 

Fig. 3, Trf..M:^-H,hlab]e mafiping. 

Moi*e complicated stiuctiires such as tables are also supportjed 
in SNMP using the tree representation. A two-tliniensional 
table with rows aiid columns can be represented by a sub- 
tree as shown in Fig. 2. Objects in the table are labeled witti 
letters A through F, antl the subtree's mapping to table form 
Is also provided. 

The ability to view a branch of the tree as a table is a usefid 
abstraction that makes it easy to orgajiiice the inlonnation 
into a readable fbnnat. Columns can represent eatej^ories 
such as the nmnber of bytes ("octet^s" in SNMP parlance) or 
Ethernet broadcasts detected on the LAN, while rows can 
represent different sample times to tirovide a historj^' of the 
network activity. In facl, this is exactly what the RMON MIB 
Iiistoiy group (described later) provides. 

Similarly, the tree-to-table mapping can be extended to 
represent three-dimensional tables as shown in Fig. 3. 

A three-dimensional table can be viewed as a collection of 
two-dimensional tables. As before, each tw^o-dimensional 
table can represent a historical sampling of network activity 
over time, l>in each table can be sLunpled at different rates. 
Such a collection of tables can, for example, hold data 
samp let! at 2-second, 30-&econd, and 1-hour intervals. The 
EM ON MIB cont^ains several instances of three-dimensional 

A limited number of data lypes are available for end nodes in 

the tree. They aie defined in FiFt' 1155, Structure and Iden- 

tifi ca t i o n of Ma nageni ent In ft mn a I / a tffor TCF/!F-Hased 

Inteniet4?A Some of the available data types are; 


Octet string 

Object, identtfiei^ 

IP address 

Netw-ork address 

Comiter (an integer from to 2^ - 1) 



Operations on tliese objects are limited. Only four operations 
are necessaiy to deal wilh the data in the SNMP tree: SET, 
GET, GET-NEXT, and TRAR 1 lie SET and GET conmumds write a 
value uito the tree (possibly creating a i^ew leaf node) or 
retrieve the value of a leaf node, re.spectively. Tlie GET- NEXT 
coiiimand* applied repeatedly, traverses the tree from left to 
right. The objects labeled with letters in Figs. 2 and f] are 
named such that GET-NEXT travei^aLs of the subtrees woultl 
retrieve the objert^s in al|>liabetic order. Tliis command aEows 
a management station to determine the scope of the data 
available in the agent. Finally, the TRAP mechanism allows 
unsohcited notificarion of unusual events. In other words, 
an agent in change of the data in an MIB can choose to alert 
a management station via a TRAP if conditions waiTant. 

Fig. 3, TYee-to-SD'table niLipping. t")]jjects D and H are <'}h£i€'ijnHt in 
Ihis pitliire. 

RMON in the HP LanProbe II 

The original HP I^inProfie contained two N'EC V50 CPUs 
which sluued the [jrocessing load and corn i nun ieated using 
shiired memory. In addition to the two niain C'Pl'Si an Intel 
82586 Ethernet chip also had access to the shared memory'. 
For the new LanProbe II, it w^as decided to swit ch to a 
single, faster CPl' to reduce the complexity of the design. 
The new Intel S259C Etliemet chip shares the bus, but trans- 
fers data into memory using DMA. The design uses a PC -AT 
chipset from Texits histmments, a 20-lMIIz Intel 80386 CPU, 
mid the hJthenu^t ciiip. 

The LanProbe It is also similar to PCs in that the DRAM is 
expandable using off-the-shelf menioiy SIMMs, The SNMP 
version of tlie LanProbe II allows IM-byte, iM-byte, and 
8M-byte configurations. No additional eonriguration is 
neefled when new nu^n^ory is added t.o the probe— all table 
sizes expand dynamically as new memory is added. 

In addition to the standard PC architecttire, L28K bytes of 
battery-backed RAM holds txinfig^iration values ar^d RMON 
configuration tables through a power cycle. This mecins that 
if powder to the probe is inteniipted wluie monitoring the 
net\\ ork, the LanPiobe resmnes monitoring with the same 
configiuation (filters, events, alarms, and other contiol 
structures) when power is restored. 

RMON Overview 

Although SNMP was iirst proposed as a simple alternative to 
the more complicated OSI management protocol CMIP, the 
RMON MIB proves that SNMP agents aren't limited to 
primitive systems. 

Tlie RMON MIB consists of nuie distinct groups; statistics, 
liistory. alarms, host, hostTopN, matrix, filters j packet cap- 
tiu'e, antl events. To be FiMON-comphant, only one or more 
of these groups is required in an RMON agent. In fact, m^iiiy 
RMON implementations do not contain all nine groups. The 
HP LanPiobe II and a small number of other implementa- 
tions, however, do suppt^rt all nine. Fig. 4 illustrates the 
functions of each of the RMON groups. 

84 Apri I 1 9&3 Hewlm [-Fae k ard Jouniij J 

)Copr. 1949-1998 Hewlett-Packard Co. 



View of 

Data Flow 

on art 



Filters capture specific packete 
and direct tlient into channels: 

Packet Capture 

Packets are storetl rnio buffers 
after flDwina through channels. 


^ On/O tf 




Fig, 4. Overview of an RMON 

An tiMON probe analyses every packet transmitted on the 
network. A great deal of work may be performed on each of 
these packets, h tiiay bo sorted by category mid taJUetl in the 
statistics and in story grtKj])s. The Et!\eniet st>iitce and des- 
tination addresses may be noted mid appropriate entries 
createti or utxiateti Ui the host table and conversation matrix. 
The |)af ket may match instil efi filters, triggering events in 
the tiroi>e mid perhaps beij\g captmed in one of the probe s 
capture hidters. Tlie 4]Vl-byt,e HP SNMP LanProbe (Release 
A.OO.O(I) keeps track of a maximum of: 

• 8 network activity histoiy reports 

• 75(J01iosls 

• 10 separate reports showing top transmitters, receivers^ etc. 

• ;30,000 separate conversations between host^ 

• 50 oiijects with settable alarm thresholds 

• 60 packet Jllters tunneling into 'iO channels^ each of which 
can si ore t jackets in one* of 12 independent capture buffers 

• 1500 log etitries of network events. 

The structure of tlie MJB produced by the Internet Engineer- 
ing Task Force (IETF) contains a number of similarities to 
the fimctionality providetl by die original Lanl^rf>be. The 
statistics, history, host, hostTopN, filtcT. and pat^ket cai>1nre 
groups all have direct analogs in lite original UmProbe, al- 
though each of Ihrae groups expands on the capabilities in 
that probe. 

The nine groups in the RMON MIB are describe<i in more 
detail in the following paragraphs. 

Statistics. This group provides an overalJ view of current 
network activity. Sampled values include octets, packets, 
error counters of various ryjjes, mid packet size distribution. 
Although this group consists of a table with one row per 
network interface (Fig. 5), the table is limited to one row in 
the LanPrtjbe Implenientation suice only tme interi:ace is 






Staiistics Table 








A. 9. 

rig. 5. liMON MtB statistics 

)Copr. 1949-1998 Hewlett-Packard Co. 

April 1093 Hi^wli'tt-I^ackiirrl .frjiima] 85 

HistofvCiiirtrol Table 

/ / / - 

^ ^ ^ i 
« ^ ^ ^ I 

Alarm Tattle 

■S -B 

^ -B :s^ 

^ J' J^ 

^ ^ ^ 
^S- P> ^ 


Hislory Table 

JV 9- s? 


5> ^ 

c? t 

Fig, 6, RMON MJB history group. The history control taijle (■ontaini^ 
one row per histoid' stufiy The history tablo is three-dimensional; it 
contains one Lwo-dimensional table for each row in Uu^ history 

control table. 

available on the probe. In effect, the statistics group provides 
a lynapshol: of current LAN activity. 

History. As its name implies, the history group provides a 
mechanism for abstracting and preserving the statisliccil 
data collected by the statistics group in tbe probe (see Fig. 6). 
The user cau speciiy a nimiber of separate history studies to 
be collected simultaneously from one or more netM-^ork in- 
terfaceSj each with a different intenal For Instance, two 
studies with inier\^al^ of -If) seconds and 1 honr can be 
created to enllect data from the same network inierface. 
The study containing 3t>second intei-val meafjurements can 
be displayed in near real tiiue on a graph showing network 
activity wMle the 1-hour measiu'ements can be uploaded 
and stored for future use to study daily or montliiy activity 
for network plaiuiing purposes. Tlie uiuubei' of inten^als 
saved in each study ctm be set by the user and is referred to 
as the nimiber of buckets m thai study. The 4M-b>te HP 
RMON LaiiFrobe can keep track of S studies siniultaneousiy, 
with a total of 550 buckets. 

Alarm. The alami group (Fig. 7) acts as the RMON probe's 
w-atchdog. Each row in the alarm table instrtuuents an object 
in the probe's MIB, U^en the value of that object exceeds or 
drops below a specined threshold , an event is activated. For 
this reason, the event group must be implemented in iuiy 
probe that includes tJie aliuin group. Each threshold can be 
specified to be either an absolute value or a delta vaiue^ 
delta meaning the difference between the previous measure- 
ment of the object and the current rtieasurenu*rit. This dis- 
tinction is necessiuy since many measureinerUs in the 
RMON MIB (Emd all those in tJie statistics group) are ai>so- 
lute counters zeroed at boot ttme and increniented there- 
afler until the counters roll over. The alarm feature allows 

Fig. 7. RMON MIB alarm group. The table contains one row for each 
object being monitored 

a network manager to set thresholds on objects such as 
etherStatsBroadcasiPkts (the number of broadcast packets de- 
tected to date J and to be notified via the trap mechanism 
when the object exceeds given limits. Alarms can be rising, 
memiing that an event is generated when a certain (rising) 
tlu-eshold is exceeded, falling, meaning tliat an event is gen- 
erated when the object's value drops below^ a certain (fall- 
ing) threshold, or both. Rising and falling thresholds are also 
used to rearm an alarm to prevent the same alarm from fir- 
ing repeatedly w^hen network activity causes a threshold to 
be crossed and recrossed rapidly. 

Host. Network managers commonly need statistics detailing 
each node in the network. If errors per second suddenly lise 
sharply, it is useful to know whether any one particular host 
is responsible for the increase. Therefore, the host group 
provides a table of hosts for each netAvork interface avail- 
able on the RMON probe. Each table contains .statistics on a 
per-no<k^ basis, including Inmsmitted and received packets 
and octets, and transmitted enors, broadcast, packet^), and 
muJticasi packets. In a fashion smiilar to more connnon data- 
bases, each host tal>le has two separate view-s, in which the 
same data is displayed in ^iifferent ways. The first view^ is 
indexed by each host's netw^ork address, providing fast ac- 
cess to a particular host s statistics if the network address is 
known. This table is sparse in the sense that tliere can be^ 
for exanxjile, up to 96 empty rows in the table between rows 
containing liost OS0009-0()2(M):3 and liost 08t)0O9-O()2I00. The 
second view is indexed by discoveiy time ortler. That is, 
host-s are entered in the table in the order in which they are 
discovered by the prol>e. This table is tliere fore densely 
packed, and is useful for management applications wisliing 
to retrieve a Ust of all hosLs without regard to host address. 
Fig. 8 shows the host tables. 

HostTopN, The huslToijN group provides just that — a numteter 
of lists of \he top N hosts in a given host table, with ordering 
criteria configured by t!ie management application (see Fig. 
9). A control table contains settings for each top-N list (or 
report), with one row^ per report. The control table holds 
infonuation on what value the report should be ordered by. 
Transmitted or received packets and octets, transmitted 
enors, broadcasts. iu\i\ multicast packets are all valid mea- 
sures by which to sort. Each row^ in the control table also 
specifies Ihe inleivai over w^iuch data for 1 he report is col- 
lected. %lien the collection period is finished, a new host- 
TopN table is created containing a sorted list of values and 
host addresses. This information is ased to discover hosts 
transmittmg tmusually large amounts of traffic or errors^ 

S6 April 199:1 Up wten-Pa<kardH Journal 

)Copr. 1949-1998 Hewlett-Packard Co. 


Host Ekrntri»f Tafare 

s s i i 

Matri)i Dontrol Table 




^ O CO 




Host Table 

'* S J* ^ i^ 
^ o ^ o o 

r ^ 

# # 

fABlm Source — DestinaEion Taiii* 

Host Time Th tile 

Slinilaf to KosI Tal»fe 

Fig. 8. RMON MIB hosl group. The host table is a sparse Lable. It is 
indexed by host address, so not ever>' row wjH esdst. Tlie host Uine 
table is siimiar to the host table but is indexed by CreationOrder instead 
of Address; hence it is densely packeci. 

providing th<? network manager with an overview of net- 
work iuiomalies at a glance. 

Matrix. Tlie matrix group charaderizes conversations be- 
tween hosts on the network. It consists of three tables: a 
control table contiiining information on a per-interface basis^ 
a tabic presenting the data from a Iransjtnlter-orienteci view 
(the sotuce-destination table ). and a Uible present ing the 
same data trom a reeeiver-orient.ed view (t he destination- 
sotirce table). Like the host tables, these are based on the 
network address of the hosts. Pig. !0 shows the matrix 
control table. 

TopN Control Table 

TopN Table 

1^ % # 
^ -F 'T * 


Fig. 9. RMON MIB hostTopN group. The TopN table is three- 
difuiMisiutial, f^ont^iining one two-diinensujnal table (report) for eaeli 
row ill the TopN control txible. The rate in each rppon nuiy refer to 
the rannher of packets sen!, or received f ir Lhe iinnibcr of octetJ^. 
errors, broadcajsts, or multicasts. 

Matrix Des^tinatinii — Source Table 

Fig. 10. RMf }N MIB matrix group. The two data tables accompany- 
ing the control table contain identical data, but one is ij^dexed by 
source address and the other by destination address. 

Fitter Packet filters and channels are included in this group, 
Filtei^ identify which packets are of special interest to the 
network manager. Packets that pass the filter test iire Tun- 
neled into channels, allowing a variety of actions for each 
such packet. Acting like a pipe in the netwtjrk plumbing, 
channels can be turned on or off, allowing or restricting 
packet Oow. The valve providing this conlrol is the channel- 
Data Control variable. When it is set. to ON, packets can flow 
tlu-ough Oie channel into jjarket capttire l)uffers or can trig- 
ger events, which can in turn create tog erdries or turn on or 
off otlier chaniuds. Whether a channel is ON or OFF, another 
variable (channelMatches) counts the packets that have been 
directed to it. A rnunber of filters cat\ he associated with 
each channel Any packet that is accepted by at. least one of 
these filters is directed l.o the channel Chatinels can choose 
instead to accept only packets that fail all of the attached 
filters. Ifsmg combinalions of tiiese conditions allows a great 
deal of flexibility. Hg. 1 1 shows the filter group. 

Packet Capture. This group (see Fig. 12) consists of buckets 
in which the packets flowing through chamiels can be 
stored. A number of capttire buffers can be actively storing 
packets at the same time. Eacrh of these capture buff ens can 
be set to lock or wrap when full, that is, the buffer can sti>p 
collecting packets when full or it can retiun to the beginning 
of the buffer and overwTite the oldest packets capttired. 
Since a wrap- when -full btiffer always contains the most re- 
cent packets ca|>tured, this featiu-e can he used as a netwt^rk 
"black box" similar in fnnction to the endless loop recorders 
fount! hi aiqjlanes. When the network crjishes ur misbe- 
haves in st^jne way, a detailed histoi^y of IAN acti\1ty is 
available for downloading and decoding for the network 

April 1993 Hewlett-Packard JounmJ 87 

)Copr. 1949-1998 Hewlett-Packard Co. 

Filler Tabid 

Evfini Table 


/ ^ ^ 

* # 

W Co ^ 

^ -^ --^ 

c <r c 



Cliatinel Tata I e 

^ ^ ^ i ^ i ^ 

iS Q AT o -J o <5^ 



ir ^ /? 



■^ *- 

Log Table 



^ W § J^ 

**l ^ ^ <J 

Fig. 11, HMON MIB filter gffmp. 

niatuiger. To allow a large iiimiber of packets to be capturedf 
buOtTs call be configiiied to save only a '*siicp" of each 
packet This can be very useful since most of the interesting 
in formation in each packet is located in a relatively small 
header at the bej^inniiig of the packet. 

Event. The event group (Fig. 13) provides a means to 
associate actions with network conditions. Events can he 
triggered either by packets flowing tlirough c-hannels or by 
alamis. hi turn, each event can fire some action within the- 
probe sucli as creating a log entr^^ or, if the event is inipor- 
tant^ a trap* Events can also turn channels on or off, acting 
as packet capture triggers. Since events can generate log 
entiies, a log table is also contained in this group, hi it, a 

Buffer Cantrol Ta£ile 

Fig. 13, RM(JN .\1IB event group. Tlie log lable is Llvree-diniensiDnal. 

Eiif'ii snhttiblp is owned by a sepanite t^vent in I lie event table. 

number of log entries can be associated with a single event. 
This group provides a great deal of flexibility for a manage- 
ment apph cation to customize the behavior of an RMON 

Programming an RMON Agent 

In some sense, a network manager niust program ai^ RMON 
agent before the agent can begin to provide useful data. As a 
simple example, history studies must be configured in the 
bi story control table before the agent will begin to build 



-5 s 





Packet Cajtture Table 



^ ^ ^ 
S ^ S ^ 

/ / i i / / 


Fig, 12, RMON JVUB packet capture gvoW- ^^^^'^^ ^^^' *>f tl>t' buffer 
control table specifies d different capture buffer. The packet capture 
table is three-dimensional, containing several two-dimensional 
tables, e^ch of which \i^ "^owned" by a row in die buffer L-ontrol table. 

A more interesting example involves setting up the probe to 
monitor the netw^ork for broadcast storms, captm"e them as 
tbey ocx'in; and store the data for later penisal. To perform 
this duly, Ihe probe must eonstantly collect packeti> from the 
network, discarding the oldest and replacing them with new 
packets. Filters must be installed that capture every packet 
and direct it dov^n a channel. Tlie channel, in turn, must, be 
diiected into a packet capture buffer created hir this pin- 
pose. The capture bidfer is set to WRAPWHENFULL (creating 
essentially a circular buffer of the latest packets) and is set 
to some limited size to reduce the total number of packets 
held at any one time, say 10 OK bytes of data. The channels 
Data Con trof setting must be ON to allow packets to flow, SitKe 
the beginning of a broadcast stomi is most interesting, we 
need some method of shutting the chai^iel off after the start 
of the stomi to preserve packets in the buffer (j.jrestimabiy 
tliose that caused the stonu). To do ibis, we'll set an alarm 
to trigger on the etherStatsBroadcastPkts coimter in the statistics 
group, liMien the rale at which that counter rises exceeds 20 
broadcast packets per second, the iUami will tiigger an 
event we've previously created. That event logs the activity 
(etherStatsBroadcastPkts h£is exceeded 20/seeond) and sends a 
trap to a mai^agement station lo alert it to the problem. 
Meanwhile, triggering the event has turned the chaimel off 
aJid packets stop Oowuig into the capture Ijuffen Later, the 
network manager can exanune network activity trends over 

S8 Apdl Um Utwh^n-Piickani Joumd 

)Copr. 1949-1998 Hewlett-Packard Co. 

the course of the stomi by looking at data in the histoo' 
group, then upload and decode the captured packers, 
incJuding whatever packet or packets initiated the stomi. 

In a different s<*enaiio. packet filtets <*aptumg packets of a 
gi^-en protocol can be diierted into a chaiinei monitored by 
an alarm. When that protocol's actj\'iry rises or falls outside 
given thresholds, logs or traps can be generated and other 
channels mmed on or off. Since alarms can be created to 
monitor any object in the RMON MTB, liie number of possible 
useful agent ronfigitrations is limited only by the ima^nation 
of the network manager. 

Future Directions 

Although the RMON MIB was originally created for Ethernet 

interfaces, the rise in popularity of the f oken-ring protocol 
will spur the need for similar monitors for these networks. 
There is work nirrently in progress that will produce an 
RMON MIBspeafiration for token-ring networks. In atkii- 
tion, SNMP version 2 has been proixjsed and is currently 
being evaluated by tlie lETR It contains several features 
missing in SNMP and useful for an RMON agent, including 
security, encryption, and bulk data retrieval. 


Despite the "simplicity'' of SNMR the RMON Mili tleinon- 
straies that SNMP agents can be complex and offer a rich 
feauire set, Tliis complexity is necessary to allow the agents 
to monitor tiie netwTjrk in a useful manner. Because of the 
progranmiabJe and inexpensive nature of RMON agents, a 
single management station can ohserve and manage a large 
network with many segments. 

A hil] description of the RMON MIB is contained in RFC 
1271 and can be obtained \1a ftp from veneraisLedu. Interested 
readers can be added to the RMON MIB mailing list by 
maiUng to nnon!Tiib-request@iarthurclaremonLedu. 


1 would like to ihank Gigi Chu and Gmy EUis for their guid- 
ance and leadership ihroughou! the project. Reva Bailey and 
Judy Tsai both contributed a great deal to the success of the 
Lan Probe n, aitd Fill Dentjon deser\^es much credit for the 
hardware design. Project managers Don Manoogian and Sud 
Verma initiated and concluded the project, respectively. 
Thanks also to Steve Hand, Steve ^^'Itten, imd Lyie Weiman. 
who worked on tlie Probe Manager user interface and had 
tlie pleasure of discovering bugs In our t^ode. Finally, th£mks 
to the entire IETF Remote Network Monitoruig Working 
(iroiip for their efforts in seeing the RMON MIB through the 
s tim dard i zai i o n p rocess* 


L S. Waldbusser Rf^mote Nefnmjii Monitoring Management bifot- 
nutfioti liftsf'^ RFC I27L Carnegie MeDon irmversity. November 


2. V. Cerf. LAB Rpcommcndatiou^sftfr fhe DftVfdopmmf offfiteniet 
Network Managemenf StattdatyU, RVV 1{)52. NR[, April lUm. 

3. W,W. Cnmdall, "Design Challenges for Distributee! L^VN Analysis," 
Hf/wk'tl-FiWknnl Journai. Vol. AS, no. L Kebniiiiy^ 19^)2, pp. G6-76, 

4. M. Hose and K. McCioghrie, Sffut'lure a fid Identiflai^Uyn ofMau- 
agtmtenl hijnrmntloyijhr TCP/IP-hthsfii Itttenwt.s, RFC 1155, Per- 
formance Systems Intei-nationai, Hu^ihehi I^AN System^s, May, 1090. 

April \m:\ I rtv% l(vt r-I'arkard Jouriiat 89 

)Copr. 1949-1998 Hewlett-Packard Co. 

The HP 64700 Embedded Debug 
Environment: A New Paradigm for 
Embedded System Integration and 

The HP 64700 embedded debug environment gives embedded system 
developers complete access to state-of-the-art real-time measurements 
and controls in addition to C and C++ static debugging capabilities on 
HP and Sun workstations. 

by Robert D. Gronlund, Richard A, Nygaard Jn, and John X Rasper 

Hardware and software developnient. for nucroprocessor 
systems embedderl in other systems and products requires 
sophisticated emulation, code development and analysis 
tools. The HP 64700 embedded debug enviroument (see Fig. 
1) is an emulation interface system designed to create a tiew 
debugging tool paradigm for embedded systems developers 
ajid iiitegrators who use emulators for today's pow^erful 
Kvbit. aJid t32-bil CISC and RISC microprocessors, Tlu^ major 
contribution of this systeui is its ability to provide not only 
the expected static, C arid Cn- laugu^e debugging capabili- 
ties for large embedded systems, but also easy access to bi\ 
extensive set of modular real -time control and analysis ca- 
pabilities, all with a common, easy-to-use XI 1 OSF/Motif 
user interface. This real-time capability together with the 
powerful IIP 64700 emulation bardw^are system sets this 

embedded debug environment apart, from other emerging 
graptucal interfaces and uitegrated software tools focused 
on embedded software development and debugging. 

Embedded System History and TVends 

Tf;ere hiis been a surge in the application of microproces- 
sors to enhance the operation of products that most people 
do not tliinls of as computers^products ranging from re- 
mote controls to the space sbuttle. Tliese products contain 
microprocessor systems embedded within them for various 
reasons inehiding costt usability, and flexii^iltty. Hence km 
embedded system Ls any microprocessor-! jased system that 
is essential to the operation of a product not thoughl; of 
primarily as a computer. 

Fig, h Full HP 64700 debug 
envirorLTTient srssion. 

90 Apri 1 1 9m J le wiett ■ Packani Journal 

)Copr. 1949-1998 Hewlett-Packard Co. 

TTie Value of Usability 

ErmjIatDfS are complex trtstmmenis thai rambir^ sofrfiisttcatsl reattlme anatysts 
with mcmpfocessor niu contfoL memojv managenent. and s^'mbolir; software 
debugging. In adjittcn to understanding the mr^X hanJwBre and applicatic^ 
sdft^ere, emulatof useis mu^ also master the nuances of aniuiator cQafiguntion, 
syrttiot refErencwg, trace sequencing, and other emulation control functions As a 
result, most erriulatofS am difficult to use 

The ongtna! HF 64000 design team was cQn<^med about this complexity, and 
made ease of use a key dement in ttre first HF 64100 system The result was a 
user interface based on softkeys It was menu-drjven and offered a hierarchical 
directed -syntaK command struaure. The ease with whsch users could si! down m 
fmnt of an HP 64100 and become productive helped taynch Ihis succeissfyl prod- 
uct. Since then, developments fn workstatjons and peFSonal computers have 
established new expectations for human interfaces. At the same lime, application 
program sjze has grown exponentially, redefining the kind of information users 
need to access to d^ug and integrate embedded systems 

Beginnmg in 1989, several research projects were initiated to better understand 
the changing requirements of embedded designers. A telephone survey of 72 
emulator users was conducted by the Gediman Research Group in 1959 One of 
their key findings was that ^'development systems are criticized for lack of speed 
,.. and diffj cult/poor user interfaces." Their findings were troubling, many owners 
had come to view emulaiofs as a tool of last resort because of their complexity. A 
customer visit program was conducted by RSiD and marketing experts in 1990. 
They interviewed 20 users of the most sophisticated H? emulator and found that 
19 did not use the full capabilities of the mstrument. largely because of interface 
and configuration compleKit/. It became cfear that the effort to create and market 
a capability is wasted if users cannot or will not access it. As a result, a product 
priced on the basis of potential performance will fall short of expectations when 
the marketplace assigns a value to it consistent with realized performance This 
finding led one designer to remark, "If a feature isn't understood, it doesn t exist ' 

Two important studies helped measure the importance of ease of use. The Tech- 
nology Research Group conducted an embedded CASE study In 19S9. When asked 

what role 14 kBf attributes played in tool seledlDn. S45 eniisd^sy^Mlif^^ 
sionats ranked ease of use mg^ important, The secor^ sunif was cofstoted bf 
Oasis Computer Solutions in 1 990 This stydy fweasured tiie impCHtarice of ease of 
use against 1 7 other lop-level requiieiBents Ease of use was mnked second, jiist 
aflsr real-time eiecution Notabfy, source-level debog capabihtv ranked third. 

As embedded software grew in compfexjty. the tools used for code developmerrt 
and debug grew more sophisticatKf Compilers replMHl assemblers, and C de- 
buggers, as a companion to emulator interfaces, were rapidly growirtg in popular- 
ity The Oasjs study and the actions of our competitors confirmed the importance 
of C debuggers to embedded designers Our C debugger had a different look and 
feel than our emulator interface, and worse, was not easy to use togetber with 
our real-time measurement capabilities. 

We were convmced that user interlace improvements were key to success, but 
still needed to choose a course gI action from several alternatives being consid- 
ered at the trme In late 1989 we commissioned a SUMM study The SUMM 
(Single Unit Market Model) study is a proprietary choice modeling technique of 
Eric Marder Associates. Inc It offers a mathematical description ol how customers 
choose products based on their desires (user needs) and be fiefs (vendor percep- 
tion) When applied to customer survey data collected in the current marketplace, 
it predicts what product customers will choose in response to changes tn product 
and/or market strategies. Based on this research, we aggregated user needs 
agamst key competitors, and created a program in January of 1^1 to improve tbe 
usability, consistency, and integration of the emulator and source debugger inter- 
faces for the HP B4700 Series emulators. Ttie result of that effort is the debug 
environment described in the accompanying article 

John D'Alessandro 
Market Research Arralyst 

Colorado Springs Divisbn 

Thronghotit ilw past de<rade. embedded systems have grown 
exponeiitJiiJly in size and complexity, driven hy Hie same sili- 
con technology that has created low-cf)st, high-perfonnanc^e 
pergonal coinpii let's, .fnst as tliis complexity has challenged 
developers of com pi iter systems and software, it fias also 
challengtHl enitiedded developetT^. These lievelopers are often 
required to gtiarantee an exacting st^mdard of real-time re- 
sponsiveness to meet operational requireme^nts. For many 
embedded devekipers, real-Lime really niatlers. 

Microprocessor emulation i^ystems first appeared in the late 
1 970s and early 1980h to address the system integration 
needs oJ' entber Ided tievelopers. ^ At that time die only tnicrO' 
processors conimer<iaJly available were relatively simple 
8-bit iniplemer^taliorts, Tln^ enibedded softwEtre usually con- 
sis ted of a fi^w bun tired 1 n a few thousand hnes of assent bier 
code that control lerl the liardware directly ^md was often an 
afterthought in the system implementation. Tbis was also a 
natural consequence of the limited address spiK^e and primi- 
tive langiuigt* tuuls ibal were availaijle with tbese prrxes- 
sors. The chalh'ngt^ thai has emerged in totlay s large, liigli- 
performance embecJded systjcms is tJte syntliesis of complex, 
stmcturefi software systems with powerfid hardware to 
meet rciil- world detnaiids and stunuli in real lime. 

In parallel with this evolution of real-time emulation capabil- 
ity, anoHier of rlebuggirig tool evolved Ifiaf basaiso had 
a rev oh i ti o 1 1 my i mpact — t he high-1 e vel hnigu age t iebugger 

(referrcKl to hereafter as the C debugger because of the prev- 
alence of the C language m embwlded development). The 
need to create and implement conH>lex software systems 
has made abstract it.>n essentiiil, tt> k*'ep develoi>er's from 
being overwhelmed, AbsirafMioii hfi.s rrininly come in the 
form r>f high-level hmguages. In embeildtHi developmenL Hie 
languagt^ that ha^ bet^ome far arid away the most poptdar is 
C, witli C++ emerging as its logical successor. 

While emiilarion interfaces were initially fociLsed on dynamic 
understanding of machine states and assembler language 
(and remain vc^ty capable at this tiisk), C debuggers were 
uiitially implemented on minicomputers to allow (ievelopers 
to tinderstand the operation of their software at the saime 
level of abstrat lion at which it was written. The capabilities 
of tnost ntodem debuggers include sU'ick backtrace display^ 
high-level data typing, complex data structure displays, high- 
level expression evaluation, and source code referencing. 

Another emergent trend in larger embedded systems has 
been the reaJ-Ume operating system f RTOS),^ This has 
served as an important point of leverage for embedded de- 
velojier-s l>y creating an arlditional level of abstraction, much 
like I ugh- level hmguagf*s. While the RTOS vendors have en- 
deavored to provide specializetl debuggers capable of mider- 
stmiding the state of stopped (static) .systems in terms Uiat 
developers can imderstaitd, they have been notably lacking 
in the provision of debuggers that, cfin provide notijntrusive, 

A I jri I 1 1 « Ki J It w k tt-Pa* rk^ird Jni im al 


)Copr. 1949-1998 Hewlett-Packard Co. 

abstracted views oif real-'time operafion — ^a Sf?emirigly logical 
reqiiircmt*nt for a rpal-time system. 

Another trend is the demand for tisability. Products that are 
laden wilfi alf the "iij^Kt" features but are effectively inacces- 
sible will likely fail in tht^ marketplace (sec **The Value of 
Usabihty" on page 91 ). Tliis has been supported by tiie emer- 
gence of graphical interface systems aimed at making pow- 
erful applications faster to learn and etisier to use. 

Finally, there has been aji emergiug trend in \hv area of 
software tool frameworks and integrated develoj)nient envi- 
ronments. Tv/Q notable leaders in this area are Bi jrlauci's 
integrated development environment on tJie PC and the HP 
Soft Bench CASE framework for tTNiX'^'-systeui-based work- 
stations. The focus of these systems has been the aiUonia- 
tion of common tasks for software development teajns and 
inereasuig the usability of common tools by reimpleuienting 
them using graphical interface technology/* 

HP 64700 Embedded Debug Eiiviroiutient 

Drawing on its roots in the original highly mtegrated HP 
64100 microprocessor development system, the HP 64700 
embedrh'd debug environment synthesizes elements from all 
of these sources In fonu a new paradigm that realizes the 
most advanced implementation to date of the "electronic 
workbench" vision tVn eml>edded systems developers as 
described by Chuck House in U}79^ Key capabilities of the 
system include: 

• A full complement of emulati on-based debugging and analy- 
sis tools inckKhng a C/C-F+ debugger, a real-time emulatiori 
control aud state analysis mterface, a tiiie real-tln^e software 
pert'ormiuu e ajuilyiser irU efface, and a tuning waveform 
analysis interface. 

• The ability to shift debugging aiui analysis views and tools 
rapidly to zoom in and out on the really hard debugging 
problems — notably problems in the re a! -lime douiaiu. 

• Advanced, XI 1 OSFAiotif user interfaces that ton form 1o 
the IBM Connuon User Access standaid and pi'ovide fast, 
consistent operation, powerful support for symbohcs, intu- 
itive system configuration, and powerful support for user 

• An adjunct set of tools inchuIlMg a detnigger simulator, a 
branch test tooL and a dynamic real-time operating system 
analysis tool (see ''A Real-Time Operating System Measure- 
ment Tool" on page 97). 

The paradigm shift embodied by the debug en\iroimient is 
the leveraging of tofjl iutegratlou t<.) allow quick perspective 
shifts to the \4ew most apiiropriate to testing the ciurent 
debug hjTiothesis — from static C and C++ tiebugging to true 
real-time measinemenLs including slate, (iming. mid software 

performance analysis. Because of the modular implementa- 
tion of the tools^ developers new to the system can start by 
simply using tiie window Oiey feel most ctimfortalile '^driving*' 
the emulator witJv. Hardware desigi^ers might choose the 
emuJator/analyzer, software designers itiight jireferlhe C 
debugger, and hcHTlwaie-sofTware integrators working on 
complex f jroblems might start with multiple wiuflows simul- 
taneously (see Fig. 1), The system provides headroom for 
future growth in a modular fasliion: add a new tmalysis 
lioard to the HP tFl7t)0 cardcage and add a window to tap its 
(;a|)abilities, or just add a \\dndow for tools not ret|Uiring 
liaitiware instnmicntation. 

Emulation Interface Evolution 

From their roots in the e^irly euudation systems and hosted 
debugging tools, emulation interfaces have evolved into two 
different primary tyjies: the enmlation/iuialysis mterface and 
the C/C++ debugger. The focus of each of the interfaces Wris 
different, as shown in Fig. 2. With the debug emiroiuneut 
these uiterfaces are now treated as complementary rather 
than con^petmg tools and can be nin sj^Tichronously and 
simultaneously witJi tlie same emulaton 

Along the way, EIP developed other new analysis technolo- 
gies h one of which was the software ] performance analyzer.'^ 
The solUvHie pt^rforniance aualyj^er' system was a totally new 
concept ir( fJie mid-1980s. 1( pro\itted the hardwme and the 
user mterface for sampled (jerfonnimce measurements. The 
the newest generation of this techiuilogy, the HP B1487 soft- 
waie performance analyzer (see article, page 107)^ adds 
new, tnie real-time , nonsampled duration measurements. 

The contriliutiou of the new HP tHTOO tk^bug en\ironment is 
the realization thai all of these capabilities are importtuitto 
the integrators of embedded systems and must be mnde 
understandable and quickly accessible, espe<:'ially for de- 
manding projects imder uitense time-to-market pressure. All 
of the elements of the system automatically work togetlier 
ami have a common look and operation model, so softw^aie 
develot>ers can more easily explore the use of emulation 
haiTiwaie hreakj)oints cuul real-time software periormance 
analysis to examine even algorithmic problems, instead of 
spending time adding elaboi'at e debugging code (such as 
printfs) to their systems. Haidware developers can become 
more productive by writing diagnostic and test code m C. 

The lismg value of making the embedded software developer 
more productive has lead us to define the debug environment 
in a somewhat broader scope than just that of traditional 
emulation. The en\ironment is structured to aOow contribu- 
tions to extend In scope beyond those that use only the 
emulation ciudcage. 

Em ittatDr/An sl^yzer 

Debugs assembly cade (can display C/C-h- source lines) 

Oe»ls witb real-lime problems 

Unite rstaitds: hits and bytes 

Excel lent measurement cajtabilrties inclutfinf stale aitil 
timing traces 

Measurements can lie taken and displayed without dis- 
turbing the real-time operation of the target systems target 
runs at lull ^peed by tlefaull 

EKceJIeni emulator conli juration central 

C/C+4 Debugger 

Debugs C prngrams 

Can only laok at static (stofiped] systems 

Understands and displays C data types and expressions 

Only static stack backtrace 

Must slE>p target execirtlofi to measure 
Imulnlor configuration "a necessary evil" 

Fig. E. CJC++ dt^hugger versu.s 
emuiator/anaI>7Le r in terf ace 


April UKi^ Hewlett -Packard Journal 

)Copr. 1949-1998 Hewlett-Packard Co. 

The Debug En\iroiuiient Connection to HP SoftBench 

HP SoftEench provides a framewori^ m which a variety of sofiware devefopment 
tools can be ptacsd.' Or^ce properly conn^ed to the SoflSEnch envtranrnent the 
tools communicaie with each othei by means of messages CommLinication wa 
message ailms m^maiim of mo^ ta^s of tht dev€!<ipmait process. m6 ttientiy 
speeds up the developrmnr iKocess The HP 647D0 dibug envifoiwn^l desentieil 
in the accampanyirig arttcle cm be confmct^ to the SoftBencfi developmen! 
envirofirnerrt to provide a SoftBeoeh emliKkiBci dBvetoprrrent ewironmeni 

The primary tools of the SoftBench emtjedded development eTtviranment mnslst 
of the SoftBench editor, the SoftBeoch static analyzei. the SoftBench buitd tool. 
and the HP 6470Q embedded debug environment j including the HP Branch Validator} 
A user can also add such tools as a canfrgurat^oo management system, SoftBench 
marl, or a complej<!ty analysis system. Almost any combination pf SoftBench tools 
can be added to the SoftBench embedded development environmsriL 

Connection of the debug environment to SoftBench is made by using the Soft- 
Bench Encapsulatortoaf, which provides a SoftBench message interface for the 
debug enviror^ment.^ The SoftBench message interface allows ihe debuy environ- 
ment to receive debug messages such as step, run, set breakpoint, load executable, 
and so on, and to send edit, build, static analysis, and other messages lo the other 
SoftBench tools. 

The SoftBench message interface for the embedded debug environment 
(DebiigWOO) acts as a translator between the SoftBench and debug environments 
(see Fig. 1 1. SoftBench messages sent to Debug647M are translated to debug 
environment commands and sent to the command parser of either the debugger or 
the emulator or both, depending on which interface is running. Once parsed, the 
commands are executed as if the user had entered ihem directly The debug envi- 
ronment, conversely can forward commands to Dehu96470D, which translates the 
commands into appropriate SoftBench messages, Simple syntax allows a user to 
fofward almost any command or message to the SoftBench environment. 

In addition to message translation, the Debug6470O encapsulation provides a 
startup inierface to the debug envirnnment This startifp interface simplifies the 

pfDcess of choosing a debug environment system and deciding which interfaces to 
start. The user simply selects a system to start artdthen the interfaces to start 
(debugger, emulator, or software f^rf0nTWK:e ^alyzer) Pressmg the start buttofi 
will start all of the resjuested itebug environriffint tntBrfaces and complete the 
connection between the SoftBench and debyg sivirwff^efrts. 

The Oebufl647fl0 message translator and startup interface ts a srmp!e program The 
Encapsulator tool made it possible to code and test this connection to SoftBench 

in aboul two months We were able to produce a prototype within one week, 
Completing the Hnal fonn of the interface was stmply a process of rriodifying the 
protot^e. Very little of the program was wasted or thrown away. In fact, our 
initial intent was to use the Encapsulaior only to create a prototype startup inter- 
face, but as has happened m the past.^ the protot/pe was so usable that we 
elected to extend the prototype rather than create a new interface from scratch 
TiTis is the second time that we used the Encapsufator to create a prototype and 
discovered that it would take less effort to extend the prototype than to create a 
complete implementation of an OSF/Motif-based interface. Our hats are off to the 
SoftBench Encapsulator. a tool thai allows a user to design an OSf/Motif mterface 
in a matter of m mutes when hours of effort would be required without it 


1 M fl Cagan, "The HP SoftBench Envirorvmenr An ArchitHittire for a Mew Generation of 

Software Tunis, Hewlett-P^vkard Jdumal W 41. no. 3, Jurve 1990. pp. 36-47 

2 B.D Fromine, "HP Encapsulatpr. Bridging the Gen-eration Gap." ibtd, pp 59-B8, 

3 D.L. Neuder, "A Test Verification Tool for C arvd C++ Programs/ Hewlett-PackBrd JoumBl, 
Vol, 42, no 2..Aprin93l. pp. 83-92 

David L. Neuder 
fiSiD Design Engineer 
Colorado Springs Division 

Fig. 1. DebuQ641Q0 SoftBench connection 
window foT the HP 54700 embedded debug 

The ability of the debug erivironment tools to connect with 
tlie HP SoftBenrh CASE framework is otie of the keys to 
tills iinpleru*fntation (see "The Dehiig Etndr'onnient Connec- 
tion to HP SoftBencii" above). Fig. 8 fijghligiils liow the de- 
bug environment tools fit into a simpliilef [ enibetftled devel- 
opment lifecyele and work with the SoftBench environment 
if available. However, since we realized that not all custom- 
ers wrjuld be asers of HP Soft Bencli. the debug environment 
trjrjlsel is designed in such a w^ay that the tools anlomati- 
caJly fonn ii powerful frnniework and cocu'dinate aniung 
tht^Hiselves using a teclumlogy spt^cilli^aliy desigiictl for this 
purpose. Tliis higtily responsive messaging capability has 

been a m^or system design challenge and subseQuent 
sections detail this technology. 

Some fuither aspecLs of this broader environment definition 
are of interest: 

Tlie debug environment has built-in capabilities to fomi a 
"mini-SoftBench" iti the areas of code editing, rebuilding, 
ajui reloading for tisers who have not adopted SoftBench. 
An optional C/C+-^ debtiggcr sinitilator allows simulation of 
target system code t>perattt>n to begin even before hardw^are 

April 1993 Hewlett-Packard Journal 93 

)Copr. 1949-1998 Hewlett-Packard Co. 


Third- Party Tools 


* Structured Analysis 


Design HPSoftBenchGraphicat * Structured D eslg n 
Tools including Static 
Analyzer and Program 

HP D/C-HH Dell ugger Simulator 

* Code ManHgemant 

C/C++ Compilers ^^^* 

1 ntngrate HP C/C^ D Bh iigg or/ 

^■""'""^ HP6«00 
HP Real-Time Emulalinn/ Daemon 
^a*lf^»s Messaging 




1^ - HP Real-Time Software 

Performance Analysis j 
* HP Branch Validator 


"^BMS = Broadcast Message Server 
""""HP SoftBench is Optional 

A graplrical bnuicJi test tool called the HP Branch Validator 
gives accurate feeciback on braiich (^overage in code 
executed by the emulator or simulator/^ 
The debug enviroiuiieut allows large teams to share re- 
sources mcluditig emulators vm the LAN. Etheniet-coiuiectt^d 
HP 64700 emulation cardcages can be controlled from across 
a building or even across the world \ia the global internet 

The debug environment iims on both HP 900(1 aiitJ Sut\ 
SPARC w^urkstations. 

System Architecture 

The debug environment uses a multiprocess arctiitecture 
with a background daemon to coorciinate the operation of 
one or more usei^ inlerface processes. A deling en\1romnent 
sessioti consists of one or more user interfaces all attached 
to tiie same emulator and coordinated by the emyJ700dmn dae- 
mon. The result is a Inglily interactive and flexible family of 
user interface products that can be joined together into a 
single session with the foDowing capabilities: 
Separate user interface products attached to the sanie 
emulator operate concurrently and cooperatively. 
Tlie ciLstomer can buy additional products later and add 
them to the system* 

HP can develoi> additional user Interfaces anci add them to a 
growitig product laitiily. 

Defects, mainten;mce, and enhancements are contained 
within the tire walls provided by the |jrocess bomidaries. 
CKeraD pcrfo nuance is improved by using UNIX' -system 
concurrency to tinieshare operations among the user 
interface windows. 

Tlie debug environment system arciiitecture has its roots m 
tlie development of the HP-l^X'^'-workstalion-based user inter- 
face for the IIP (i4700 series of microprocessor emulators, ' 
In turn, this \vas based on the interface pioneered by the IIP 
134100 microprocessor developmcmt station in 1979 and later 
ported to the IIP-LDC operating system in 1986.® This user 

Fig. 3. T\[e t:)TLl)cdtifn1 ^Ipveiop- 
rnent. lifecyrile find [IP fj4700 
products ; 

Interface operated in a character screen and used syntax- 
directed softkeys to prompt the user iti the cotmnand line. 

Two goals were estabhshed for the apphcation of the origi- 
nal HP 64100 user mterface to IIP 64700 Series etuulators: 
cijnsistency m look and feel and support, for niodultu ity in 
adding new types of user interfaces* 

At the timet additional user interfaces were envisioned to 
support hardw^are timing analysis, software performance 
analysis, and of course, C language debugging capability. All 
of tJiese w^ere to operate concurrently on the workstatioti 
host W'liile comiected to the same HP 647t)0 emulator card- 
cage. X Window support, was hmited to the use of terminal 
window s tor roncunetvl operation of the chaiacter-based 
user interfates. This produrr was released early ui 19B9 with 
the emulator/analyzer user interface only. The timing at^alyzer 
windoW' soon followed. Tire debugger remained a sep innate 
product mi til the debug en\4ronment was released. 

Tlie debug environnient architecture described here extends 
t he original one to support the additional information shar- 
ing expected in an OSF/Motif environment while niainlahi- 
hig Ijackw^ard compatibility with the original products (see 
Pig. 4). Consistency and backward compatibility remained 
essential objectives. Tlie effortis applied in the OSF/Motif- 
based user interface to maintain consistency with the earlier 
softkey-driven user interface are described elsewhere m this 
article. Tlie urt deriving architect lue that allows both OSF/ 
Motif and r^on-OSF/Motif user interfaces to operate coiv- 
current.Iy in a single session is described next. 

Multiprocess Architecture 

A multiprocess arcliitecture pre.sents several hindamentaJ 
challet^ges w^hen applied to a real-time iiistiTmient product 
such as an emulator. Tlie user expects the 'live" look iuid 
feel of a benchtop instmment front panel. This means that 
all parts of the user interface must update concurrently 
whenever new information becomes available and command 

94 Apri 1 1 993 He wiet t ■ Pac kard Jo e i n lal 

)Copr. 1949-1998 Hewlett-Packard Co. 

rm mttmf mmy gm i igM th i^yni ii ii 

, ntMHhf tMpSirt I DI«#n£C 

«U«d| Rmao >9^S«<ll«c IKi#Sr«PC rDfi*^¥ton 

1^ I CMhiiCI Pvmn E tAcVtnci 

J mtm I oi>«a j umo \ wt^fi^ 

Cbtru or S^Littu 

I OtOf ipT^i^ rd land 

.c - itr* 1 ThjJ "Se^ @ecrs£ ^bfc arc ^«t« ur 

»01^ QKT^. J3«e i«W ]»d«t* -r c^rd 

♦#1* eeiS54 ISaa leJS sprue ^ ward 

Cmnwnit; jfMini |H«c^ dnw: |e»l'4» p^vnw^ jQcv t« sixj lOttr 

Fig. 4. The debug environment 
supports both the earlier soflkey 
interface and the new OSF/Mutlf 
interface, represented here by a 
graphical emulator/analyzen 

entry must always be enabled. Suppiyiiig tiiis operatioii 
requires solutionis to several problems: 
Arbitrating access to the shared emulator and analysis 

D LSI ribu ting notification to all windows of changes to the 
state of the hai'dware and of the session 
Managing session information, including the current working 
directoiy, tlie name of the program loaded into tlie emulator, 
and so on 

Perfomiing polling operations reciuired for the session but 
not the exclusive interest of aiiy one user ntterface. This m- 
cliides polUnj^ for emulator and analyzer status and sinnilated 
1/0 transfers 

Perfomung lengthy operations in background, such as up- 
loading trace data and notifying the user interfaces upon 

The debug en\irormient uses an event-driven messaging 
system coordii^atcd by a daemon lo conduct a session. This 
is shown tn Fig. 5, It is similar to die broadcast message 
server used by the HP Visual User Environment'' and the 
SoftBench system."^ However, unlike the broadcast message 
server, the daemon in the debug environment also operates 
as a peer of its clients in its connection to the emulator 
hardware and in its data processing activities related to 
emulation hardwiU'e polling. Each process, including the 
daemon, has a direct connection to the commmucations 
channel attached to the emulator as well as a connection to 
the message chat me 1 anchtjred by the daemon. Let*s discuss 
the conununications chaimel first. 

Emulator Communicatioiis 

The physical chajinel to the enmlator can be either a dedi- 
cated serial line or a network connection via sockets over 
the LAN. Conununications are not fnmteled through the 
daemon to avoid the overhead of multiple process context 
switches and multiple buffer copies for each transaction witii 
the hardware. Instead, a kernel semaphore is used to aibi- 
trate owmersMp of the cJiannel Once the chaimel is obtauied, 
ownership is retained until the complete transaction (or 
atomic: set of txansactions) with the enmlator is finished. At 

this level the daemon Is a peer of the other user interface 
processes with no special privileges or responsibilities. 


Semaphore-based arbitration offers different advantages for 
serial and socket coi^nections to the emulator In the case of 
a serial chaimel, the semaphore keeps multiple processes 
from intermi[igling their tiaffic on the single physical chan- 
nel, hi the case of a LAN-based socket, this cannot happen. 
Tl^ere us a different socket for each process comiected to 
the emulator However, one and only one socket can be ac- 
tive at any given time since the emulator serv^es each socket 
in a round-robin niiiimer This is because the emulator is 
inherently a shared resource that cannot be reentrantly ac- 
cessed. By continuing to use a semaphore to control access 
to the emulator^ each process blocks at the level of the 
semaphore operation until the emulator is available. This 
makes it much easlet^ to define appropriate timeouts for 
each stage of a t ransaction. Blocking on the semaphore is 
allowed lo contituie uidefinitely whereas blocking on the 
reply lo a command times out to detect faults such as com- 
mtmications failures. In either case, the user can abort a 
tnutsaction by pressing Control-C in the user interface. 

In addition to the semaphore associated with the communica- 
tions channel to the emulator, another semaphore is used as a 
comit of how many processes aie cttrrently running in a ses- 
sion. This includes the daemon and all its clients. Each pro- 
cess increments the value of the semaphore when it starts. 
The operating system automatically decrements it when a 
process exits. This is used for status checking and as part of 
the locking system to prevent other tisers from accidentally 
disturbing a session in progress. 

System Start 

Most daemon-based systems re<iuire the daemon to be ex- 
plicitly started by the user or Uie system administrator and 
to remain mrming until explicitly terminated. The start and 
shutdo^^m are typically added to boot scripts tiiat mn when 
the workstation is rebooted. This w^as deemed to be unac- 
ceptable not only because of the additional complexity 

April 1993 He wietr Packard Journal 95 

)Copr. 1949-1998 Hewlett-Packard Co. 


User Interfaces 
jclients E}f daemon} 

directly associated with the daemon, indicates that the 
daemon is running. It tias three states: none^ starting, and 
running. This is used to detect and resolve race conditions 
that can occur if iwo or more user iiiterface-s are staited 
simultaneously and eacii tries to start the daemon. Once the 
daemon is running this semaphore is used to avoid tiie over- 
liead of attempting to start another one. 




Message Classes: 
Sessiun Events 

Target Processor Status Changes 
Target System Evefits 
Svmbi}l Datebase Status 
Simubted I/O Displav Output 
Simulated I/O Keyboard Input 
Simulated I/O Status 
Trace Analyser Status 
Trace Analyser Data Available 
Software Peilomianca Artalyzer 

User Interface Conffguration Hints 
Command Forwarding 



Virtual Semaphores 

Commi^ni eat ions Channel 
jLAN Socket or RS-232) 

Pig. 5. Debug envjroninent iniiltiprocess architecture. 

exposed to the end user, but also because of the system re- 
sources that \\'oiild be tied up permaiienily hy each daemon. 
Instead, the daemon for an emulation session is started au- 
tomatically by the first client to nm and exits automaticaJly 
when the last client in tlie session ends. A third semaphore. 

Messajje Distribution Channel 

The other chaimel in Fig. 5 is the nie.ssage distribution chkm- 
ncl. This channel is different from tiie commimications 
chamiei in that the daemon has unique responsibilities for 
message distribution. Ail event messages are fiist routed to 
the daenton for processing. After processing the daemon 
forvtards a copy of each (possibly modified) event message 
to each interested client. The client that generated the mes- 
sage does not act upon it imtil it comes back from the dae- 
mon. This is another aspect of pacing the session to ensure 
that all clients act upon all events in the same order. It also 
simplifies client design in that, no distinction is made be- 
tween events generated within a client and those generated 
elsewhere, hi either case a client receives an event message 
and acts upon it. 

Message Subscription 

Wliich events is a chcnt interested in? No cUent supports all 
of the features of the debug en\ironmenL Routing all events 
to all clients would result in much more message traffic than 
is necessaiy. Most messages would simply be Ignored. 
Kvents in ll)e debug environment ai'e grouped mto classes 
(see the list in Bg. 5). When a client starts, the only class it 
receives by default is the Session Events class. Events m this 
class incUide notification of session state and changes to the 
current working director^^ 

Clients subscribe to additional classes of events by sending 
a channel protocol message to the daemon hsting the 
classes desired. Classes may also be deleted, but this feature 
is not used by any current debug environment clients. Two 
things happen when a client subscribes to a new class of 
messages. First, that client is added to the distribiilion list 
tor that class. Second, a copy of the nKist recent instajice of 
each eveitt in Umt class is sent to the client. Some events are 
purely transitory (e.g., step taken) whereas others represent 
current values of retained state information (e.g., target pro- 
cessor status). It is the larter that aie echoed to each newly 
subscribed clienl . 

The client makes no special qtieries for this to happen. 
Instead, the client is automatically brought up to date with 
all olher clients already in the session. FVom the pei-spective 
of the client there is no difference between a regenerated 
message and one being freshly distributed. In a query-based 
approach the newly started client w^ould specLfically ask the 
daemon for each piece of current state uifonuation it 
needed. Tliis was rejected on the groimds that tills would 
require a special body of software m each client tmd special 
support in the daemon for a one-time need. Ensuring that 
the client software was comijlele was seen as an ongoing 
soiuce of maintenance and defects. 

(continued on page 9S) 

96 A\m\ 199a Hewl<*( r Pac k ard .loiimal 

)Copr. 1949-1998 Hewlett-Packard Co. 

A Real-Time Operating System Measurement Tool 

Th€ rBal't3fEie operating system IRTOSI measurement too I of the HP 647D0 em- 
bedded delMjg e^viTOnment uses the ©T^ulation bus anaty^et and the software 
performance artaly^er id capture operating sysiem software activir^ in real limg. It 
wQfics with the HP &47tKJ Series stiulation traca analyzer and includes a spectallv 
developed inverse assembler that uses the trace display to show ^^ram flow 
informatim The trace display is eas]ly readable and includes a fully inierpreted 
djsplay of all parameters passed into and retumed from the BIDS service calls 
along with arry other pertinent data (see Ftg. 1] The captured and displayed data 
IS a senes of memory writes to a data table. These writes can contain mfom^tion 
about an operating system service call that was |iist e^secuted or a task switch 
that ]u5t occurred. 

The tBse measurement thai is provided by itte RTTOS tool Is the ability to trace 

task switching, Tasl^ switches are always a concern of an RTOS devetoper. When 
did they occur^ In what order'? Where within the application^ The basic power of 
an emiilatton analyzer is appfopnate for capturing thfs data. 

To capture task switches, a feature common to RTOS kernels is used. This feature 
fs the ability^ of the user to define a rouhne that will he called every hme a task 
switch occurs [or when a task starts! These routines are callecf csiioul rouiines. A 
caliout rouhne is defined in the kernel's conf iguratinn table by placing the starting 
address of a function in a specific place in the table. Whenever a task switch 
occurs, just before the new task is started, a subroutine call is issued that jumps 
to the defined address. The caliout routines are passed two input parameters 
consisting of task control block pointers of the tasks that are being exited and 
entered Within the task control blocks^ a unjque ID can be found fur each task. 

To provide measurement data, unit^ue memory locations signifying a task's entry 
and exit are defined and linked mto an application A caliout routine is written to 
take the pointer to the task control block being switched out of, find its task ID, 
and then write that ID to the extt location. A similar scenario applies tor the task 
being entered, If the analyzer is set to capture only writes to the entry and exit 
locations, the result is a display showing the time any task was exited and the 
time any task was entered. If the analvzer is set to capture other states, they are 
shown relative to the entries and exits of the tasks and the flow of task e;5ecution 
can be followed. This provides a limited display of the RTOS interaction. 

Many important events also occur at the C interface library. This is a standard 
piece of assembly code for an RTOS application, often provided by the RTOS 
vendor, that allows an application to make C function calls to the operating sys- 
tem. A function is provided for each available RTOS call to take the parameters off 
the stack and place them into registers. One of the registers, normally DO for 
68XXX family processors, is loaded with a function code and a trap instruction 
causes a jump to the RTOS kernel. The RTOS kernel looks al DO to determine what 
call is being made and processes the data m the registers accordingfy Before a 
return to the function occurs — and it may not happen until other tasks have been 
run — registers are loaded with return values and the return to the function occurs 
right after the trap instruction. 

Just tjefore the trap to the RTOS occurs, virfi^ all of the regrsters are loaded wtth 
the input data, a simple move multiple instruction (MOV€M in B8G00 assemhiy 
languafe) causes all of the data passing between the application atid the RTOS to 
be written to a data t^le T^e same thing is done on itie return When these 
writes occur all of the data can be captured by the analyzsr. Thus, all of the itans- 
actions between a task and the HTflS are available along with the times at vvtiich 
they occurred To provide a memory destinatiof* for these wt ites. a data table was 
created Thus, a fairly hill set of data can be captured by the analyzer with a single 
spec ificat tan of the data table range. 

The captured data is displayed through an inverse assenibier Although called an 
inverse assembler, there is no reason why it needs to output assembly code, and 

in this case, it is more of an inverse interpreter The interpreter reads through the 
set of states captured by the analyzer and is able to display the data found in any 
order and with any chosen ASCII text, With this technology, a trace can be set up 
to capture all of the writes to the data table, interpret them, and display them in a 
very readable form On the display there can be single lines for task entries or 
exits, lines for every function call and return showing all of the input and output 
parameters, highlighted error return lines, parameter values decoded into English 
equivalents, and even stack information. Enough infonnation can be displayed to 
give a user a complete knowledge of the Interaction between an application and 
the RTOS kernel 

Display of the RTOS trace is instantly available and a user is able to switch be. 

tween normal trace display and RTOS display A user displaying a captured RTOS 
trace.! which consists of writes to the data table) using the normal inverse assem- 
bler will only see meaningless data and address values. Using tfie RTOS inverse 
interpreter function calls with parameters, task switches, and stack information 
are displayed, 

The data table created for the RTOS measurement tool has memory locations for 
each defined function calf to the RTOS. There are entries for calls to the function 
and returns from the function, Each entry is allocated as much memory as is 
needed to hold the full set of parameter data. Specific addresses for each function 
entry and exit are defined so that when the interpreter is interpreting the captured 
state addresses, it knows exactly which function's data it is going to display 
Beyond the entries for the functions, there are extra entries for task entry and exit, 
operating system overhead, tool intrusion, clock ticks, stack infurmahon, and 
user-defined entries. 

The stack infonnation is an important addition to the capability of the RTOS tool 
Stacks are always a concern, and when implementing RTOS applications, a user has 
to declare the sue of each stack for each task. Stack problems are always difficult 
to debug, but when multiple stacks are used within a single application, the prob- 
lems multiply. To instrument the supplied code for slack tracking, memory space is 
reserved for each task. Each tasks space is referred to as a bucket, Within each 
task's bucket, there is space to store stack information. A task start caliout routine 
stores the stack sire and stack base in the bucket When a task switch occurs, the 

Trace lis! 

Qff set ^ 

nesl-Tiine Operating Sys^Bm 

with Syinhob 


->sm_ident(naFne='s«m1',n ode^^^flOOOOODOl 
<-sni irfenr[SMid=0tHICO0OQ) 
-> sm_p(SMidxt)O0CO0t)0.NOWAtT) 

■i4J17 -> ev_receive1evst£B:0OO1i, 

4>03f Exiting Task : paal' 

40^ ENTERING TASK: sllk^ 

44135 STACK BYTES LEFT ON ENTRY: Supr tXlOOOl 00 User 000001 CC 

44M3 <-cv sefid(} 

4{I4S ->q receive(qid=0a040{X)0:cssl',WAIIF0REVEfl) 

■HKl Exiting Task : silk' 

i0^ E UJE RING TASK : casp' 

Mi^re Data Offscreen 

Time Cnunt 


TG.4 ^s 
124,0 MS 

ItlO Mi 

1.01 ms 


11.1 MS 

23A MS 

aJ8 MS 
11.1 fis 

Fig- 1. Real-time Dperating sy^^tem measu la- 
ment tnol trace display 

April 1093 Hewlett-Packard .lotimal §7 

)Copr. 1949-1998 Hewlett-Packard Co. 


TalilB Data Wrties 

Data Writes Task 
aitd Reads Buckets 

Rg, 2. fleal-time operating system measurement tool data flD\fl^ 

switch caitout routine gets the stack informatJDn from the bucl^et and the stack 
information from the current task control block. With both seis of information, the 
foutine can write to the data table the current stack status. Depending on the 
RTOS kernel being iFsed iwhjch affects the data available a1 start times and 
switch times), the number of bytes used on the stack, the number of bytes kfx on 
the stack, or the current stack pointer value can be written to ihe special entnes m 
the data table This data can then be displayed by the interpreter every Lime a task 
switch occurs, which is very useful for following stacks and determining where a 
problem might he occurring. By editing the supplied command files, a user can 
track a specific task from the point where its remaining stack becomes too small 
artd then follow the actions that cause a possible stack cyerflow. 

Fig. 2 shows the data flow of the flTOS measurertienttool, 

Software Performance Aoatyzer Support 

The HP 61487 software performance analyzer (see article, page 107}, a pfug-in 
card for the HP 54700 emulation system, can provide valuable operating system- 
level profiling measurements. Beyond providing dynamic histograms of task exe- 
cution, the number of times each task is run can be displayed, providing valuable 
information on system thrashing. Also, the number of times each separate operat- 
ing system service call is invoked from an application can he tracked, helping to 
isolate bottlenecks from overused system features. 

For software parformance analysis support for the RTOS tool, a littte extra Instru- 
menlalion needs to be done, The software performance analyzer uses separate 
memory locations for the start and end of each ifvterval it is measuring. Since each 
task must be defined as a unique interval, each task must have its own unique 
start and end memory entries in its defined bucket. [This data area is application 
dependent and must be modified with the applications task IDs. | Writes to these 
entries signify a task being set to running or blocked respectively The call out 
routine is able to write to these umque locations depending on which tasks are 
switchmg. By using the task IDs as an index to the task data buckets, the switch 
callout routine can write to the entry and exit positions of a task's bucJiet, effec- 
lively startmg and stopping the software performance analyier duration limer for 
each task that starts running or becomes blocked, respective ty. 

With this instrumentation, the software performance analyzer can display cfy nam ic 
histograms of the running tasks, The user can watch as a task starts to use more 
time and its histogram begins to §row relative to the other tasks. Thts can give the 
user insight into the detailed working of an application. 

Command Files and Action Keys 

RTOS measurements are made easy to access by use of the action keys provided 
by the debug environment interface. To run a measurement the user simply points 
and clicks on the appropriate action key [which runs a command filal, and the 
setup IS done automatically. If parameters are required, the user is prompted for 
diem. In the graphical interface, these prompts appear as dialog boxes in which 
the user can either type or cut and paste the required parameters The user can 
modify the command files provided and set up action keys for user-defined RT0S 
measurements, The command files provided with the RTOS tool represent a set of 
measurements that a typical designer of an RTOS -based application would he 
likely to need. 


The RTOS measurement tool uses the complete capabilities of the emulator to 
provide measurements for RTOS-based applications. Same instrumentation must 
be done, which does produce some intrusion, but the results are well worth the 
minimal extra time. A compfete understanding of the interaction between an 
application and a RTOS kernel is possible Users will learn things about the way 
their applications run that they could not learn by any other means. 


Special thanks to Eric Ku2:ora who provided the spark, many ideas, and much 
ancouragemeni for the RTOS project. 

Mike Dotseth 

Software Development Engineer 

Colorado Springs Division 

Message Queue Implenientatioii 

Tlie message channel is implemented as a sitigle UNIX- 
system message queue. A message qtieiie offers low over- 
head and simple operation as long as message disTnbiition is 
limited to a single host. Sockets, and domaiuf sockets in 
particular, were not mature when this choice was made 
(1987)h Today the choice is still appropriate since there is no 
current need to distribute a single debug cnwomnent session 
across multiple platfomis. The X Window^ System and vaii- 
ous network services provide support for remote network 
access to a session. 

The message type attribute provided on each message is 
defined as the combination of a client address and a packet 
tj^pe. The address is assigned when a client attaches to the 
daemon. Tiie packer type distinguishes between connectioni 

event, acknow-ledgment, and chi:mjiel protocol packets^ Un- 
like a socket-based channel, the presence of the message 
type alJows message acknowledgments to be read from the 
head of the queue even if other messages destined for the 
same client were placed in the queue earlier 

Most routine transmissions from clients to the daemon on 
the message queue arc actually sjuchronouSj with the 
sender w^aiting for an acknow ledgement that the message 
w^as received and processed by the daemort. This was found 
to be necessary* for pacing the system i^roperly. t -lients can- 
not over rim the daemon since each transmission is acknow^ 1- 
edged and, just as important, a sequence of events generated 
in one cUent stays in proper sequence with events generated 
in other clients. 

t Domain sockets are sockets- aptjmned far ihroughpur when both ends of the cannecfitan reside 
ofi the same node in the network. 

BB .April 1993 Hewlett-Packard J oumal 

)Copr. 1949-1998 Hewlett-Packard Co. 

Avoiding Deadlock 

This picture of s>Tichroiioiis transTmssions from each client 
to the daemon and a.s>7ichronoiis transmissions from the 
daemon to its clients is a Onie loo simple, however. The 
most important exception (xxtiirs when ouilrjple transactions 
with rhe emulator occur atontically \dUiin a single owner- 
ship of tlie channel semaphore. The daenion may ver>^ well 
be blocked on the channel semaphore since it performs poll- 
ing activities as well as message distribution. If a client 
attempts to forward an event message to the daemoit syn- 
chronously from within the channel lock, the acknowledg- 
ment will never arri\ e since the daemon is blocked on the 
channel — a classic deadlock. 

Messages are only sent within a channel lock when multiple 
commands mtist be treated atomically, such as during 
emulation coniiguration. Therefore, acknowledgment is dis- 
abled w^hen messages are sent from within a channel lock. 
However, syitchionism is not lost. The clieru tJiat sent the 
unacknowledged messages is required to send one more 
synchronously to enstire that it pattses tmtil all messages are 
processed by the daemon- 

In addition, if another interface issues a commaixd that 
does not require accessing the hard%vare, it will not hang 
even if this requires sending the daenmn a message. Tliis is 
because the daemon is designed lo suspend its chaimel wait 
temporarily, process software-ortly messages (including any 
acknowiedgments}j and then resume the channel wait. 

Messaging Citizenship and Command Forwarding 

The message queue provitles the transijort layer for distrib- 
uting events within the session. Subscription and distribu- 
tion have already been discussed. But witich events should 
be distri tinted? \^1iiclt are of session-wide importance? 
Wtticli are not? The definition of session -wide interest is 
termed nfUenship. The designer of each user interface is 
responsible for going through the list of events supp*-^r1ed by 
tiie daeruon and dctennining when, if ever, the user inter- 
face might generate the event. An exarni)le is the user com- 
mand to step to the next source line m the target program. 
Each progrant view, whetlter it is at the source level, die 
assembly level, or the machine level, subscriljes to the step 
taken event message. Therefore, each place in the user in- 
terface of each window thai can generate a program step 
must also generate the event message that annomices that 
the step was taken. Ai^y cuiTently active program \dew will 
then be notiHed of tJie step and take whatever actions are 
required to update its window contents, 

A second example of a session-wide concept is the current 
working directory. It was too confusing (atid only miirginally 
tiseful) to allow each window to have its own value for the 
current directory. Therefore, each user interface is required 
to notify the daemon, via the apjiropriate event message, 
whenever the tiser changes directories. Each user irUerface 
responds to this event by making the system call to update 
its own current working directory. The OSF/Motif user inter- 
faces also respond by updating any file selection dialogs that 
are currently raised fis well 

A design rtile related to this citizenship retiutremeni is lo 
defer the secondary effects of a user coinnumd uiUil tht^ 
event message arrives back from the daemon, bi the case nf 
a progiain step, the step is performed immediately and, ii' 

successful, an ei^nt message is sent. The secondary effects 
of display updates are deferred until the event message is 
received back from the daemon. In this way. the cUent re- 
sponds to user-created e\ ents in the same way whetlter they 
were initiated locally or in a different aser interface in the 
same session. This approach veiy modular 
code — the step code needs to know nothing al>oui memory 
or source display ctide. The only software connection 
between the modules is through messages. 

Another aspect of citizenship is related to the operation of 
command processing in the HP 64700 Series emulators. 
Each transaction with the emulator consists of a command, 
its reply, and any asynchronotis e^'cnts that ntay have oc- 
curred in the etnulator since the pre\ious trattsaction. An 
as>Tichronous event message is generated wlten the target 
program luts a breakpoint, accesses guarded memory, and 
so on. .\s mentioned above, to improve overall efficiency, 
each user interface process has direct access to the emula- 
tor. However. asjTichronous messages mtLst be distributed 
throughout the session to tipdate displays and perform other 
actions, Ftiithertnore. the contertts of the asyTichronous 
message may be of Jio local interest whatsoever For exam- 
ple, the software peri'oi-mance anal>^er w-indow has no local 
response to a softw aie breakpoint message. The citlzensMp 
nUe is that any such messages are stripped frotti the com- 
ntand reply and forw^arded to the daemon for distribution. 
No local action is taken tmril the message is distributed 
back to the client by the daenioiK F'ortunately. asyitchronotts 
messages are rare relative to the ntintber of tJansactions 
with the emulator Thus, a brealqioint event returned to the 
software perft>miance analyzer whtdow is dealt with in ex- 
actly the same way as if it were returned to the debuggei\ It 
is not actefi upon innncdiateiy, but is sen! If> the daenion and 
routed to inierested clients, one of W'luch is certainly tlie 

An important conse<iuence of this design is that the system 
implements a bithrectional facility called comtuiuul fon\';ml- 
ing in eat h inlcrface. Each interface is capable of sending 
miy legal c^onunant^t to any other interface niniiing in the 
session, and any itUerface is always able (except for nonnal 
blockages) to receive and execute commai^ds sent from 
other ititeifaces. This exposes almost ttu limited p{>ssibilities 
to advanced system users, including the creation of complex 
commajid scripts capable of automated testing using the 
measurement strengths of sevenil windows at once. 

Managing Message Queue Overflows 

Dtiring a session, any of the user inteii'ace clients may be 
stispended at any time to perform shell escapes or other 
commands of unknown duration. Arrangements must be 
made to deal with event messages botmd for a susiie Titled 
process, ff the message quetie fills uii wilh messages for a 
suspended (or otherw^ise busy) user interface, the entire 
session would freeze tmtil those ntessages were read^ The 
daemon woukl block waiting for space to beconie available, 
and the session would come to a halt — another deadlock. 

The approach taken to deal wilh tliis situation is as follows. 
UlK>n the nu^ssage queue im ftill, the daemon [mils the f>ldest 
message fi-om tlieqtieue m\i\ determines which client it is 
lor. .AJl messages for that client are then ptiUed from the 
queue and placed into a temporary file, as are all future 

April m^ iyw\cU-Par\i;m\ .3ot(nt;i| 9fl 

)Copr. 1949-1998 Hewlett-Packard Co. 

messages until ftirther notice. A token is then placed into tiie 
queue to be read by tlie client when it resumes operation. 
This token indicates tiiat messages have been redirected 
and provides the naine of the temporary file in which the 
messages are being put. When tlie client eventually returns 
from the suspension, it reads this token instead of km actual 
event message. The client acts on this by in torn ring the dae- 
mon fin an acknowledged, synchrojiouslrj\jLsartiori) that it 
is ready to resume and then reads the backlog of messages 
from the temporary file. The file is removed when all mes- 
sages in it are processed. The daemon then resumes the use 
of the message queue for iJiis cUent. This approach imposes 
overhead only w^hen a backlog actually develops. Ai^ altenia- 
tive would be to inform the daemon of every user interface 
operation that might take too long, discontinuing the use of 
the message queue until the operation is complete. Not only 
does tfiis add overhead to every operation, but it rehes on 
the developer to identify all such situations. 

One aspect of tJ\e need to swap out messages from the queue 
is unique to the use of a single message queue as the trans- 
port mechanism. The queue nmy become full w-hen any non- 
suspended client attempts to transmit a message. However, 
only the daemon can actually swap out messages. Since the 
queue is full it cannot be used to notify the daemon of the 
need to sw^ap out messages. Instead, a UNIX-system signal, 
SIGUSR2, is sent from the client that defected the futl queue 
to the daemon. Mien the daemon receives this sigUciJ it 
aborts its current task (if rniy) and inunediately swaps out 
the oldest messages from the queue. 

The daemon is also capable of sw^apping out all messages 
directed to itself if no other messages are found in tlie queue. 
This can happen in the rare situation where there is high 
messaging activity and the daemon gets temporarily beliind 
in processing its own messages. 

Other Daemon Functions 

Other tasks are also performed by the daemon. Some events 
returned by the enudator as asynchionous messages require 
further processing before transmission to the user mterface 
cheats. An example of this is the receipt of an imknowTi soft- 
w^are breakpoint message. Tills meaJis thai a break]joint that 
was not set by the emulator was executed by the target pro- 
gram. The run-time library provided with the HP Advanced 
Cross Language System (AxLS) compiler uses this mecha- 
nism to announce the completion of a target program fre- 
tm-n from mainO or call to exitO) and for faults such as divide 
by zero or any other kind of message that the monitor or 
user code wants to send to the liost. The conversion from 
the raw message to its final form is performed in the dae- 
mon before the message is copied for ^hstribution. Each 
class of messages is provided witli a filter function, which is 
invoked to perform this operation. The filter can either de- 
lete the message. jTiodify l\ by obtaining additional hifomia- 
tion from tlie emulation system, or change it to a different 
message altogether (see Fig, 6). 

Another task performed by the daemon is polling for status 
changes related to certaui classes of event messages. This is 
closely related to the filter fruictions suice the filter func- 
tions accumulate the retained state infonnatioii needed to 
bring newly attached chents up to date. Just as there is a 
filter function foi^ each class of messages, there is also a 

Due Message Describing the Event 
Address: DaeiTien 

Message Queue 

To Each Interested 

Client (May Be the 


N Message^r One per Client 
Address: £ach Client 
Subscribed to this Class 



N Messages, 

One for each Hegenerated Event 
[n tbis Class of Messages 
Address: Newly Attached Client 

(Invoked When a 

Client Subscribes 

to a New Class of 


Fig. 6. Debyg environnieiil message routing jukJ processing, 

subscription processing fut^ction for each class. This hmc- 
tioii is invoked each time a client, subscribes (or desub- 
scribes ) to a specific message class as described above. In 
the case of a new subscription tlie appropriate event mes- 
sages arv recreated mid sent specifically to the new client 
wiiuiow hi addition to this, some classes of messages require 
slat us ptjiiiug to (ietenniue state changes. Emulator and 
analyzer status are tvt^o examples of this. FotJing is only en- 
abled when one or more clients are curt enl.Iy subscribed to 
the associated message class. Thus, the fust client to sub- 
scribe to a given class causes polling for status changes 
related to that class to stait and the last client to remove 
itself from the subscription List causes status polling to stop, 
A new event message is transmitted each time a change iu 
Stat t IS is detected. 

Usability Issues 

Usabihty is a mi^or concern and expectation witlt any prod- 
uct. This is especially true of products \^dth computer-based 
graphical user interfaces. The intense competition among 
comi>uter vendors to impro\ e the toolkits and stjde guides 
available to developers of applications running on their plat- 
forms is testimony to this (act. The decision was made early 
in the development of the debug environ tnent to use the 
OSF/Motif toolkit and to conform ro the IBM C onnnon User 
Access standard^ which applies to personal computers as 
w^ell as to workstations. This decision was necessary but by 
no means sufncieril to complete the design of the graphical 
user interface for the debug environment- Adtlitional factors 
considered were: 

100 April 199.3 HcwlPtt-Parkard Journal 

)Copr. 1949-1998 Hewlett-Packard Co. 

' ConcuiTent oi>eration of a debugger and aii emulator style 


Application of direct nianipulaiion concepts 

(Jperatioi! of scrollable windows with unbounded contents 

Provision for user-supplied macros on pushbuttons or action 


• Retention of all user-l>ped responses for later use 
» Provision of an immediate int^errupl or abort on lengthy 


Compadbility mth the previous comniand-line-based user 


Synchronous Wndow Operation 

There are nvo mayor issues associated with the concurrent 
operation of a debugger imd im enuilat or style itser interface 
in the same session. The first is that a tiebugger pauses 
whenever the teirget program is rmining, whereas the enuila- 
tor style is to stay alive while ttie target jirogram runs. This 
allows the user to peek atiiJ poke while the target systeni is 
i-muiing (using the HP dual-pcjn emulation memory architec- 
ture), albeit at a low level Tl>e debugger pauses since most of 
its displays are based upon the cunent state of the program 
stack, ^'v'hieli is essentiaDy imdefined while the target |>ro- 
grain is ruiunng. Tlierefore, allo%ving the emiilatoj/iiiiatyzer 
window to continue while the debugger/enuilalor wirulow is 
paused is a useful feature. The problem is lliat I lie debugger 
must now^ be mutii more robust and able to tiaitdle the situa- 
tion when the target program is stalled (or stopped) from 
the eniulator/ajialj^er wintlow. Fortunate Jy, the event sys- 
tem described previously in this article provides a natural 
way to deal with I his. The debugger responds to the "Taiget 
prognmi now running'' event by going to its paused state. 
When the "Targe! program ncjw paused "" event arrives 1 he 
debugger queries the taiget for its stack iincl register contents 
and displays the current state. 

Tliis ability of the ''live-key bo anf interfaces (such as the 
emulator/analyzer ;md the"e perfomtance analyzer) 
to t-ontiinie otieration wlule tlie debugger is paused tiecause 
of a running user pt ograjn is crucial to the [jower of the ile- 
bug enwtjmnent. If the user's code has gone astray the tie- 
bugger may be useless in helpmg to imderstanii the real prob- 
lem since it requires hneraction with the emulation monitor 
CO tie to do anything. It might be more appropriate to take 
some state traces to look at the errant operating situation. 

Tiie emulator/analyzer allows the user to take the traces and 
display them all without disturbing the openUion of the user 
coiJe (wliich may be disturbed enough already). The individ- 
ual interface windows complement each other naturally and 
powerfully in this manner 

Tlie other issue concerning the concurrent operation of the 
debugger and the emulator i^lndows Ls the difference in 
viewpoints. The debugger is typically used vvitli a source- 
level view of the target program, whereas the emulator win- 
dow is typicaDy used for a tnaclune or nuxed C and assembly 
source view. Operations such as snigie-stepping tlie target 
program and setting breakpoints are defined (or both vlewrj. 
However, not all opera tU>ns at the low nutchine level corre- 
spond to those at the source level. Again, the event system is 
used to communicate these events and care was taken to 
ensure proper operation. 

Pop- up Menus 

Direct Jiianip illation is fimflamental to most successful 
graphical user interface con\ponents such as sliders, scroll 
bars, toggle buttons, aiKl resize handles. It allows the user to 
point at tlie item lu he chtmged and |4> change it witii im- 
mediate feedback, hidirect methotis. such as t>ull-down 
menu systems and pushbuttons, are useful when a direct 
luediod would be confusing or obscure. The debug environ- 
men! iLses a combination of these methods. Fmlhcmiore, an 
additional direct manipulation inetliod is used to supple- 
ment some functions available in the puil-dowm menu sys- 
tem: the pop-ut> menu.^ -^ Pop-up menus cm\ be obsture since 
not all portions <jf the user mterface suppt>ri them. The user 
may become lost trying to remember when a [>tjt^-tit> is avail- 
able and when it Ls not. hi the debug em iroumetit the avail- 
ability of a pop-up menu is annoimced by a change of tlie 
mouse sprite. Normally, the position of the mouse is indi- 
cated by an aiTow-shaped sprite, Whenevci the nuiuse is 
over a display aiea that sujiports a pot)-up menu the sprite is 
chai^ged to a small hand shaiie, as in tlie left haliof Fig. T, 
Holding the right mouse button down ftn' more thtm one 
second will ratse the pop- up me mi. The choices on the uienu 
atn^ly l<^ 'be liiglilighted lint^ in the display (see the rii^ht haJf 
of Pig. 7), Tliese are chosen to make the most frequently 
used operations t|uickly available. In the source window, for 
example, these incltule setting mid c1e;:U"ing breakpt)inis, 
raising the text editor to exaiuine or modify the source file 

100 Ufhl le ( true? 
102— i 

1 rtt errupt_3l m{ anun_check3 ) I 
if (graph) -^ 

graph_daTa( J ; 
pro c_sp8C Cf i c i ) ; 

uuhi le (true) 


interrupt ^tm(&num_ch«icks); 

graph_datfl( ) ; 
prQc_specl f 1 e( ) » 

,ete Breakpoint 

^ Journa 1- 

(Twnp) Break inodule updaTe_sys line 56 
Progran Run Untl 1 &\ ^ 

(Temp) Break module metn line 103 

<Tismp) Break module update_sys [ &<ffr Attached M 
> Program Run Unti 1 81 

fTem^) Break modijle main line 

Fig, 7. Hand ctirsDr indiLmss poji-up [ntiui civviilHbHify. 

April mm llrwktr l^arkarif.kninial 101 

)Copr. 1949-1998 Hewlett-Packard Co. 

A New Perspective on Emulation Hardware Modularity 

The HP 64?D0 microprocessor developrriRnt system is g mnduiar mstnjmentirame 
that allows users to cSo in-circuil harttware and software debugging of an em- 
becided target system, The cardcage (Fig. 1 ) accommodates a variety of opiional 
cards to support all of the customer's in-circuit debugging needs These iricfude 
microprocessor bus analyzers, software performance analyzers, emulation control 
cards, and communication cards. The graphical user interface running on the 
user's host computer communicates with the emulation frame over a IAN or serial 
cof>neciicin_ The frame Ihen connects to an emulation probe board over a custom 
high-speed cable. Finally, this probe is plugged into the user's larget system in 
place of the target nrncro processor This architecLure allows the user to measure 
and control the target system from ihe familiar and easy-to-use interface on the 
host computer. 

Several advances in integration technology have allowed us lo rearchiiect the HP 
64700 emulation system arsd achieve a subsiantial reduction in system cost. 
Traditionally, the run control and memory subsystems of m in -circuit emulator 
required several through-hole boards in the systenn cardcage. Now all of this is 
integrated onto a double-sided surface mount probe card about one-fourth the 
Size. The lesult is a product with essentially the same feature set for about half 
the cost. 

As processor clock speeds increased in the 19aOs, we recogrti?ed that same micro- 
processor signals had to be handled as close to the target system as possible 
However, we were still very sensitive to the mechanical intrusion of the emulation 
probe. We simply could not put a substantial amount of circuitry on the probe 
because this would prevent us from physically plugging into target systems. Thus 

Fig* 1* HPB47QD microprocessor develdpment system emulatcrr carifcage and probe. 

the first active probe emulators were architected to have as little hardware on the 
probe board as possible. This required us to use very expensive cabling to route 
high-speed processor signals up lO the emulation frame and hack. It also put a stnct 
limit on the length of the cable because of concerns over signal ptiopagation delay. 

Recent advances in integration, including fine-pitch surface mount technotogy and 
highly integrated, high-speed SIMMs, have caused us to rethink our philosophy 
about active probes for emulation Today's emulation control probe handles all of 
the processor-specihc signals right at the target system for maximum electrical 
transparency We are also able to put up to 8 megabytes of emulatfon memory on 
the probe. This typically allows us to operate out of emulation memory with zero 
wait states (i.e., as fast as the processor can access the target memory system) 

We are certainly still sensitive to the mechanical intrusion that even this relatively 
small probe may introduce. Therefore,, we have developed a fteJtible adapter thai can 
be connected from the emulation control probe to the target system. This com- 
bination allows us to plug into virtually any target system with minimal elBctrical 
and mechanical inhusion 

Handling high-speed, process or- specific signals on the emulation control probe 
has allowed us to rearchatect the rest of the emulation system to be substantially 
more generic and less expensive. Rrst of all, we are able to use much cheaper 
cables because instead of sendmg high-speed sjgnals from the target system to 
the cardcage and hack, we have simply extended the backpfane of the cardcage 
down to the probe. 

Secondly, the emulation hardware in the cardcage is no longer specific to a target 
processor, A generic analysis bus generation card in the frame can be customized 
via firmware in flashable ROMs in conjunction with programmable hardware to 
work with any of the emulation control probes 

Aside from redocing the system cost, isolating the processor-specific aspects of 
the emulation system to a single probe board substantially lowers the cost of 
upgrading an emulator to work with a new processor For example, to convert from 
a 68020 emulator to an 80960SA emulator, the customer only needs tu buy a new 
emulahon control probe along with new software for a fraction of Ihe cost of 
buying an entire new system. 

Another advantage of the new architecture is time to maricet. The development 
effort to design and implement a new emulation control probe is far iess than that 
required to design a traditional emulator The result is that we are able to support 
more of ttie popular microprocessors for embedded systems at a much lower cost, 

Ttiomas C. Ferguson 

Software Development Engineer 
Colorado Springs Division 

c^ntatiiing the Tirw in the display, attaching a macro, running 
until tlie tiighliglited line, aiu] starting a trace f>f progi^ani 
activity from the highlighted litie in the program. In any 
event, if the tisernever discovers the existence of popup 
meniLS in the product at all, all operations availalile on the 
pop- up n^eniis are also a\'ailable from the piill-do%\ii menn 
system. Thus, pop-up mentis are an auxiliary, expert mode 
of operation- 

Tiie behavior of the contents of the pop-up menu associatecl 
^ith each type of display follows the same rules as the con- 
tents of pull-down menus. Tlie entnes in the menu are the 
sanie no matter what Ime in the display is highlighted. If an 
individual item is not appropriate for the higlilighted line it 
is halftone d to show that it does not apply. Related choices 
are grouped togethcn An additional rule is that the fiTSX item 
Is always the one chosen if the user does a "quick click' of 
tlie right mouse button. For example, tlie pop-up menu in 

Fig. 7 shows Set/Delete Breakpoint as the first item. This Ls the 
default action taken if the user holds the right mouse button 
for less than a second (a quick click). These rules, together 
with the behavior rjf the mouse sprite, lead to a short learning 
time atid accurate operation of ihe pop-up menus. 

Sticky Scroll Bars 

Many of the ciisplays iii the debug environment provide 
scrolling capability to billow the user to view the data of in- 
terest. However, the direct application of OSF/Motif scroll 
bars is very difficult in some cases. One example is the dis- 
play of memoiy contetils in the target system. The display 
covers the entire address space of the target processor — up 
10 fE>ur gigabytes. Another example is lite display of trace 
dala (the results of a tiace of program execution). Here the 
length is bounded by the size of the trace buffer in the ana- 
lyzer, but the number of display Unes is a nonlinear function 

102 April mm HpwlFtM'arkard ioiirnal 

)Copr. 1949-1998 Hewlett-Packard Co. 

of ihe display mode and may be ^'er> expeixsfve in time to 
compute. For example, in one mode the display is restricted 
to only the source lines that correspond to prograni execu- 
tion in the trace bufien Each source line reference n^ay rej> 
resent one lo fifty lines of text. Each entiy^ in the trace 
buffer may correspond to zero, one, or even fifty source 
lines including leading comments. 

Thus, m the first case the number of lines is known but 
enormoas. and in the second case the number of lines is 
unknown but too large to compute quickly. The solution is a 
"sticky slider" together with arrow Inittons u> peribmi the 
home-up and honie-dowTi functions. The stick>- shder acts 
Uke a spring-loaded retunvtix-enier linear control. Dragging 
d^e slider upwards scrolls the list a few hues, just like im 
ordinary scroll bar slider. Dragging it back to the center 
restores the original position of the list. Releasing the slider 
allows it to return to the center of the shder troughs ready 
for the next operation. An additional feature is that (iragging 
and liolding the slider against either Limit causes reiietitive 
scrolling for browsing. The basis for tlus design is that nK>st 
list scrolhng operations are of hnuted range iUid it is \'er>^ 
ijupottaiit to be a]:)Ie lo undo a previous scroll in a predict- 
able way. The absolute position feedback formerly provided 
by the position of the shder is conveyed in the hst itself: by 
tlie memory address coliuun in llie memory data display and 
by the trace list number offset in the trace data display. 

User Customizatian 

Customization of tlie user utterface t^ fit the specific needs 
of each user was a high priority, X Window System re- 
sources pro\ide one level of customization. The debug envi- 
ronment supplies over 50 application resomTcs to aEow iiser 
adjustment of display size, timeouts (e.g.. the pop-up menu 
hold time}, the initial state of the conmiand line, the uiitial 
contents of selection lists, preferred text editor, and more. 
Perhaps the most significant i}f these is the action key 
i>anel — -a set of buttons fcjr which the labels and Ihe associ- 
ateti actions are both specified by the end user. Tlic action is 
Ln the form of a co nun and to execute when the buttotx is 
pressed. One or more itdws of action keys can be specified by 
the user. A default set is shipped for eacli window in the 
debug environment, j\n action key cat; tie deli tier! iu remake 
and reload the taiget progrmn, to reset and njn the target 
system, to specify £md stall orien-ased traces, to di.splay data, 
or to perform any other frettuently retjtiired task, Tlte t om- 
mand for im action key can use t he current contents of the 
cut buffer as part of the command. Syntactically, this is indi- 
cated by the use of an empty pair of parentheses. (), in the 
command text. Thus, the user can cut the name of a vjuiable 
in the display and dien use an actitju key as aii operator ^n 
it, perhaps to initiate a trat-e of ah accesses to that variable. 

Acceleration for Symbolic Operations 

■^ryping entries in ati otherwise fully graphical user interface 
Vim be an (Umoyaru^e. 'lyping the siinu' entr>^ many times 
fUiring a session can be truly aggravating. Tfie debug envi- 
ronment solves this problem by pruvitlirig a recall dialog fo! 
nearly every text entity field in the itser interface. This in- 
chides the commanci line. Hie select itni diah^gs, the cut 
buffer, and others. Each rime a text ^nwry is made ami ap- 
plied it is saved in tlie associated recall dialog. PiuUiermore, 

apphcation X Ulnflow System resources permit the initial- 
ization of each f*f these recall dialogs v\ith a user-specified 
list. For example, the Previous Files section of the file selection 
dialog can be iiurialized with the names of conmnonly loaded 
absolute files, no matter what director>^ they are in. Tlie re- 
call bu^er for die cut btiffer can be inirialized with com- 
monly used s>inbob. nuch as mam. loadHardware. and so on. 

To ease the pain of Eong. difficult debugging sessions, the 
cuirent contents of each recall buffer are saved whenever the 
session is ended for continuation. Because the windows are 
designe<i to be \iewec! sinujltaneously. each wuhIow usc^s the 
system messaging facihtj^ to echo cuts to its local cut buffer 
to all other sessioit windows. This allows symbols and ex- 
pressions to be shared easily \\ith tether wuidows where they 
may be useful in following a complex debug hypothesis. 

Signal Support for X Windows 

In most powerful aijp^'t *il^'^>i^s^ the user mtist be able to can- 
cel lengthy operations. The X Wintiow System provides sev- 
eral mechanisms to allow^ this. I'nforttuuitejy^ none is based 
on the L'NIX-system sigJial mechanism. The internals of the 
debug environment were reused tlirecUy from the older 
character-based user mteiiace, which uses the signal mecha- 
nism to allow the user to abort lengthy operations. The user 
is told to '* Press Lontrol-C to abort," The termmal driver 
uitercepts die Comrol-C chiuacter and issues an interrupt sig- 
nal to the process. The X Window System makes no such 
provision for special handling of certain characters in this 
way. Furthermore^ the ren\ote chent/server relationship per- 
mitted by the X Window System rules out any straightforward 

The solution taken t)y the delmg environment is shown in 
Fig. S. A special -putpose daemon, XSigServe, is nut in the 
background oti tlie satne host that is luiuiing the debug envi- 
ronment. This is not necessajlly the same host that: is dis- 
playing the session (the latter is knowTi iis the X serv'er 
host)- The X Window System allows many different clients 
to receive keyixianl events from the same window. XSigServe 

Remaie VVorkstation or Host 
Running ttie Debug Envirannienl 




Canfi action 

Fig. 8. iJibiii^ eiiviiotuntHtt XSiflSm? arc:hitecliire. 

Apiit mm I Ic'wiel f Pac k:jr(t .Jounml 103 

)Copr. 1949-1998 Hewlett-Packard Co. 

takes advantage of this 1 o nujiiitor the characfers Ixjuiul for 
each debiig eiiviromnent window. When a ContrQl-C arrives, 
XSigServe sends a SIGINT signal to the process associated with 
the X window in which the Control-C was pressed. The pro- 
cess tliat (iwiis iIh^ window nmy be blocked or busy in a low- 
level operation when this occurs. Ordinmly it would not see 
t-he Control- C until the operation is coniijletcd. However, the 
SiGINT is delivered from XSigServe iirnneciiately and the opera- 
tion cMi be aborted. The window ajid process IDs as well lit^ 
the characters and signals to be rnoiiilored Ijy XSigServe arc 
passed from each debug enmonniei>t U) XSigServe when the 
debug environ nteni is siarled hy using <m applicat.ion-spec^ilic 
property on the rooi wijuinw to find first XSigServe and then 
client messages to pass the infonnation. 

Backward Compatibility 

C'oni|jatibility with previous user interfaces for the HP B470tf 
was very iniporlajit. There is a large installed base ui now 
expert users of the older interface. An important objective 
was to allow* these expert users to transition Ut the new, 
graphical J nser interlace at a pace of their own choosing. 
The most Siiliem feature of the previous interface Lti rliis 
regard was the soft key-driven command line area. Eight 
softkeys prompted the user vdth choices that were legal at 
each point in the conunand entry process, including modifi- 
cations in the middle of the coiuiiiand. This eonmiaiid line 
area was retained in the debug environ mein as an cjpiional 
region at tlie bottom of each window, fiiilially off, t lie cojiv 
mand line area is added automati rally when fJie user types 
in the tli splay area of the user interface. It can also i:ie added 
liy using aJi entry in the pull-down menu system. From the 
keybtiartl the command line operates exacdy the same way 
as m the older eharactei-btised product. Habits and tricks 
teamed by users stilt apply. In addition, enhancements were 
made to t^ke advantage (jf Itie mouse aiut the cut buffer. Tlie 
mouse can be used to position the text enrsor and lo per- 
form cut and paste operations. A graphical recall buffer is 
provided to hold previously issued commands. 

In addition to these directly visil>le usahitity issues, the ini- 
plementation dealt with two hidden prol>)enis. FirsL the de- 
bug enviroiunent reuses the substantial body of software that 
implemented the previous screen-oriented, hut character- 
based, user interface. Second, the work required to dehver 
over a dozen different | Jrothicts eontauung four different 
types of user Interface windf.^wy (the debugger/emidator, 
emulator/analyzer, soft ware perronnanc e ajudyzer. ajid 
emulation conllguration windows} within a yem^ had to 
be minimized. 

The original ASCII-oriented product core used a package 
based on curses to write character strings to specified loca- 
tions on the ternunal screen. The product core was isolated 
from curses by a display utility libraiy lliat nuuiaged virtual 
screens and provided prmtf functionality to write into those 
screens. Since curses is based on support for tenuinals, the 
notion of d^iiajiiic screen resiznig was iu>t built into the dis- 
play lihrajy nor' into the product core. The stJategy adopted 
for the debug environment wtis to replace curses and the 
other diivei^ under the display utility library with look- 
ahkes that actually write to X windows. Ncidier tlie thsplay 
package nor the product core was mocUfitHi to accoinptisli 
this. Unfortunately, the prohibition against dynmnic seieen 
resizing had to stay in effect. Thus, the main display area in 

Manage a ite or more rows of user-defiited acfian kev^^ 

BfQwse a text file or an array of strings. Provide ttie mea^nsto save itie 
cunieiits lo another file. 

Pfesentttie user with a ctiotce of one of H aUernatives. 


aisplay llie most rec^mly cut text and provide a recall birfferlo seleci 
previousty cut text strings. 


Allow ttie itserto select a filefroni itie cur root dtrectory or front the lisi 
of previously selected files. Change directory whenever the current 
working directory event m^s^agf; is rDceived. 


A simple help system with a lisi of topics and a file lor each- An 
XcBrDvuser Js used to view the help text. 


iVtanage a pop-up menu, including timeouts and callbacks. 


lUfatntain a list of previously selected items in a scrotlable recalt dialog. 

Simitar to XnRecsii, except the list is fixed at startup. 

A character-bi^si&d, random- ace ess text display, including higihlightiflgK 
text cutting, andfiop-up menu support. 

Fig. 9. Dffljug f nviryjintent user iitierface contponerit hierarchy. 

the debug environnient caiuiot l:>e ititeractively resized by 
the user Instead, the size of the witidovv is fixed by applica- 
tion resoiuces (luies find colunuis) timl the uset can place m 
an Xdefaults file to customize, Windows can be ended and 
restarted ea^iily for resi^sing wittiont disturbing the state of 
the del)uggi!ig session. 

User Interface Components 

The strategy taken to minimize the amotuit of work required 
to produce tlie plethora of profluct^s required was to creale 
liser interface components. Each component is a software 
object built from OSF/Motif widgt»ts and perhaps other com- 
ponents (see Fij^, 9)- Some are very sunple. such as the rectitl 
dialog arul tlie act ion keys. Otliei^, such as the text window 
ftia! siippoiis the display package, aie quite complex. The 
piit^lic inif ! hire for each requires no detailed knowledge uf 
the X Window System or OSF/Modi' operations internal to 
the component, except itiat certaiii tjperations, such as raise 

104 .\piil 1 003 lie wlen Pat: kar d Jo un lal 

)Copr. 1949-1998 Hewlett-Packard Co. 

aiid lower, an? specific to grapliicaJ components in general. 
Tlie iise of these components even for \^er>^ simple opera- 
tions, produces consist en cj^ "by construction*' in all of tlie 
products bastKl on them- 

Debugger Macro System 

A ver%' pi)\^'erful dehuggmg feature provided by the debugger/ 
eniiiialor is the use of predefined and user-defined macros. 
Unfortunately, the use of this featiue in previous debugger 
versions was hobbled by user unfamiliarity wilh the built-in 
macros and a poor interface for the enf o' t^^ ^^^^^ macros. 
Tlie addition of tfie graphical features to the debugger gave 
us a chance to clean up tlus interface, and pro%ides a good 
example of how the debug en\4ronment makes the debugging 
task more friendly. 

Debugger macros look like (.' functions; they have input 
parameters, return a value, have local variables, and contain 
C expressions ant! siateruenis. In afidiUon. debugger com- 
mands can be em bed tied wiibiii I be macro. Within a macro ^ 
taiget pro|*nuu variables, tielmgger variables, and processor 
registers am be referenced, and variables local to the macro 
can f>e defined. Macros can be called from an expression, 
mcliiding ex'pressions within a macro, although tbey cannot 
be called recimsively Since they can call other macros, anti 
one of the built-in macros allows forwi^arding commands to 
any of the other concurrent interfaces, debugger macros 
can even cause a command to be executeti in a different 

Macros have the foUowtng uses within the detmgger: tbey 
can be called directly to execute a complex series of debug- 
ger commands, they can be called after a breakpoint or step 
command In implement complex or data driven brealq^oints. 
anfi they can be used !o |)alch target code without recompil- 
ing. To imj>lenrent (.<jriiplex bieakpoints, a macro can be 
attached to a breakpoint (t> be called when th(^ breakpoint 
is hit. The niacro return value will then be checked^ and if 
uonxero, the program will resume execution at thf-^cunent 
i n st rue l h > i ^ p< > i u l e r Pt i j g ram execi Jti o n w il 1 s t oj i (and h 
message will be generated ) if die retmn value is VA^rrh T\\\h 
feature is used to patch target code by attaching tlit^ patch 
macro at the staii of the improper code, executing the new 
co<ie witt\in the macro, setting the instruction pointer to 
point to the end of the improper code, and ret timing a n on- 
line ro value to continue execution at that poirtt , MafTos can 

also be attached to every program step using the Step TWttt> 
Macro menu selection to form debugger assertions, as in 
most host 'based debugger. 

Before the debug environntent, using the macros took a 
level of skill few users mastered. For example, in the code 
fragment shown in Fig. 10, to cause program execution to 
cease at line 104 when the variable Tium_checks Is equal lo 10, 
the user needed to remember diat a macro could be attached, 
remember the macro name when, and remember the t>T>e of 
t>arameter it takes, resulting in the command: 

Brealcpoint instructic^n r1D4;wtien(num_checks^^l0l. 

Even more difHcult was creating a user-defined macro to 
accomplish the same task. This required the user to execute 
the command Dehugger Macro Add im stopO and then enter the 
body of the macro in the journal window: 


if tnum_checks -= 10) 

return (01; 


If an enor was encountered following entr^^ of the macro 
body (say the user missiielled nLm_checks as njm_cks). tlien the 
entire macro had to be reentered. This was not particularly 

The graplucal version of the new debugger supports these 
uses by providing a selection dialog of built-in and user- 
defined [uacros (Fig. 10). This dialog shows the defined 
macros aud their parameters, ^ind whether tbey are built-in 
or user jtiacros. The selected mac ros rnri be edited (if a user 
macro), called, or attached to a breakpoint line, with the 
tJarameters specified in the dialog. Edit ing of a user macTo 
takes place in a temiinal window using the editor that the 
user bas spec ified in the resoun e file. If a syntax error is 
detected in the macro afi<v' editing, the user is given a 
chance to edit agiiin, with the rursor positioned on the line 
containing the error. The graphic^al debugger provides itiree 
sample user macros, which can be used ;is templates by I be 
user to create rnacrt js. 

Macro editing and selection are also supported by several 
pull-<lowTi menus. User-<Jefined macros can be stored into a 

Fig. 10. Mat nj diaiugaystenL 

April {P^U\ 1 wii>t \ Par karc I J m ma! 1 05 

)Copr. 1949-1998 Hewlett-Packard Co. 

file by using the* Rle-*StDre-*Usef_Define[J Mecros file selection 
dialog, and can be restored using the Ftle^Load^UserDefined 
Macros file selection dialog. These dialogs allow the user to 
save macros before exiting a debug session and restore 
them upon staituig a new session. Tliis feature was very 
difficult to use with the nongraphical interface and resulted 
in a great deal of Inist ration with the interface when a great 
amount of time was sjient enttniiig macros only to lose them 
upon ending the debug session. 


The HP (>47()0 embedded debug environment provides a ver>' 
pow^erfiil and automatically integivited suite of debugging 
tools for embedded system development teams using emula- 
tors. The al>ility^ of tliis system to move back and foith rajudly 
between static iuid real-lime fiebugging and the power of its 
c^midatifjii and meLLSurc^K nt hiudwar <* make it suitable for 
even the most difficult emliedded system debugging prob- 
lems, lis ability to mtej^rate with tiu^ IIP SoftBench CASE 
framework allows natiual extensions to handle advanced 
enibedded soft waie devcloijment using largei' teams. It is 
tlesigned to fit the needs of advanced embedded developei"s 
and excels at meetuig tlie challenge of delivering quality 
real-time systems luuler severe time-to-market pressmes. 

Ackn o wle dgme n ts 

We would like to acknowdedge tJie \ision, determinatiou and 
understanding of Dave Richey imd Tom Kraemer. Without 
their supportt the creation of this system would have been 
impossible. Specific aiul well -deserved thanks go to NhuTfred 
Anidt and Mike I pham for key contnbiitlous when the jfoing 
was tough. Special mentions should go to Sherry Adaii; 
Cheryl Browii, Denny DeBoer, Joe Hawk, Tim Clianibers, 
Tom Bateha. and Bniee Kosbab, Eric Kuzara and his group 
also provided key help and counsel. And as always, the 

nuiiketing, quality, and majuifacturing organizations made 
things w^ork when all else f^iiled, especially Tom Rogers, 
Maiueen Strong, Chuck Rice, and Blaise Cop eland. 


1. T. Saponasimd B. Kerr, "Uigic Dpveiopment System Accelerates 
M i c ratt t 111 pi \ I i^T Sysl etn Design/ Uetvhtf-Pfi t -kn t -d Joi f i v n^ . Vo LSI, 
no. 10, thtobcr 19H0, t^p. 3'i;]. 

2. T. Sperry mid G. Bay, "HeahTiine Opeiatinj* iSystcms," Embedd^id, 
Si/st4mif^ F^^tngm mm i ng. Vol 5, nn. 1, Jimuary 19JI2, pp. B7-71. 

n. MR, C'agan, "Tlie HP SoftBon< h Rinironment; An Architecture for 
a New Geno ration of H^jftwaro Torils," Hewlelf-Packatd Joifntftf, 
Vol 41, no. IX Juiie y[m\ pp. :iti-i7. 

4. C-. House, "V^ieupoints — ^Chuck House on tjie EU*c(roMk' Bench/ 
Hcwhtt-Packant JournuL Vol. 31. no. 10, Octobt^r 1980, pp. :^0-32. 

5, G. Ham Lit or I, el ai^ "An Elect mnk' Tool Ibr Analyzing Software 
Perfomiance,'' Hnvktl-PackatdJoitnuii, Vol. 33, no. 6. June 1984, 
pp, 26-32. 

ti. DX. Neuder, '*A Test Verification Tool for C and C++ Programs," 

Hetvfett-Parkmxl Jmmml, Vol. 42, no. 2, Ai>ril 1JJ91, ijp. 83-JJ2, 

7. W,A. Fischt^r, Jr., "Most Indcpcndi^nf Etnulator St.>ftw;ire Arc'hitec- 

turc," Ilfivlift-Parkfitfl dnurtnil. Vol. 89, no. B, Dec em her H^J^H, pp. 


S. J.B. Donnelly, et al, "Emulators for Microprocessor System Devel- 

opnienl," Hfnvhdl-Fm'kard Jouniaf, Vol. 31, no. 10, October 1980, 

pp. 13-20. 

9. M.A C^hampino, "A Visual User Interface for the HP-TX and Ho- 
main Operating Systems," Hewlett-Packard Jonnifii, Vol. l:^, no. 1, 
Febmai^ 1991, pp. 884)9. 

10. J. Seymour, "New Interface Dilemmas," PC Magazine, July 1992, 
pp. 99-100. 

HP-UX IS bas^ ort and is cDnipatitilR v/ith UNIX System labDratanes' UNIX' opef^tijig system 
It aKQ complies with X/Open's* XPG3. POSIX 1D03 t and SVID2 mierfaca speciiitatmns. 

UiyiX 13 a regisisred tradematk of UNfX System Labaratorfes inc. in the U.S.A. and nther 

K/Open is s trademarlt of X./Open Cofupany Limited m the UK and other countnes 

1 0€ .^pril 1 rJ93 He wtett'PackanJ Jounia I 

)Copr. 1949-1998 Hewlett-Packard Co. 

Software Performance Analysis of 
Real-Time Embedded Systems 

The HP B1487 software performance analyzer is a plug-in card for the HP 
64700 emulator system. It makes activity and interval measurements on 
instrumented code for embedded microprocessor systems. The design is 
able to deal with difficult analysis situations involving caches and 

by Andrew J, Blasciak, Da\id L. Neuder^ and Arnold S. Berger 

How call code writ i en by 15 or more individual program- 
mers, with Ihe number of lines of source code extending 
into the hundreds of thousands, be analj^ed mui ojitiniii^ed? 
Problems that arise ihrough tlie subtle interactions of tnaj^y 
different modules of code iire in the realm of the HP B1487 
software perfonnance ai^aly^er, TIte HP B1487 consists of 
ail oiiiion card for the HP (i47(J()A enmlation cardcage and 
analysis software for HP 9000 Series 300 and 700 work- 
stations and the Sun Microsystems SPxAJ^Cstation. 

Fig. 1 shows the HP B1487 user interface. This interface 
operates under the HP 64700 debug environment, which is 
described in the article on page 90. 

The first software performance aiialyzer for embedded 
systems design was the HP 643 10 A, ati option card for tlie 
HP B4000 family tjf microprocessor development products. 
I sing 1 he rnicroj>rocessor emulator as the input device, the 
HP 643 lOA moninired the memory and 1/f ) addresses that 
were output by llic micro processor imder emidation. A local 

processor on the softwjire performance andy^/er would cycle 
the analyzer through as many as 16 preselected address 
ranges, slopping at each range for a user-specified period of 
time. Any time the value of the address on tlie emulation 
processor fell \\it]iin the range currendy being monitored, a 
counter was incremented. After all ranges w^ere monitored, 
the entry point into this list of ranges would be randomly 
selected and the process w^ould start, all over again. 

The HP M310A could monitor program activity, memory 
activity^ function duration, and intermodule linkage. iVl- 
T hough it collected data in real time (the emulation proces- 
sor was never stopped to collect data), the data ihat it gath- 
ered was essentially stiitislical in nature. Memory activity 
could be analyzed only if it occurred when the analyzer was 
looking at the pailicuhir location where the activity oc- 
curretl If a program ran long enough, on the average enough 
data could he gathered to give an accurate picture of tlie 
efficiency of execution of the code under analysis. All of the 

H gw liitt Pai^tnl Perfdrmartce Anatyzer tzodlacf (iiiBi3(l2| 

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Action keys: | <Oeiii0> | Praflte jFrogMtiv% | 

j c your Key > jFunc Puntion | Stop ProlHe { Vftfj 

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[rerfoniuLiirf' analyzer tLser 

April 1 m:] Hv wIpt t f^atbird .tm im ft \ 1 07 

)Copr. 1949-1998 Hewlett-Packard Co. 

measurements made by the HP 6431 OA were statistically 
sanipled This analyzer Iiad some severe limitations that are 
addressed by the IIP B1487 analyzer. 

The HP B1487 analyzer can perform real-tiine, nonsaniplerl 
measuremeTits. This gives tfie imnlyzi^v the capability of re- 
cording at'cesses lo every address thai tlie emulation micro- 
processor requests. Thus, extremely low-duty-cycle events 
can be readily tracked and analyzed. These types of events, 
such as interrupls from the outside world, were %^eiy difficult 
to catch with statistical sampling methods. 

Modem microprocessors are rnuc ti mare complex in their 
operation than the processors that the HP f>4t31UA had to deal 
with. Modem proce^ors implement techniques such as pre- 
fetclihig, pipelines, and caches to speed up their operations. 
These tecluuques are used because accesses to the outside 
w^orld, such as RAM and ROM memories, aie ijiherently 
slower than intern ai accesses. Tire re fore, the procf^ssor at- 
tempts to mmimize the need to fetch inslmctions from ex- 
ternal memory. As a result , accesses to external memory are 
decoupled from the sequence of execution of the fetched 

Caches present a severe challenge for a software perfor- 
niance analyzer A cache is a data and/or instniction uiemory 
within the microprocessor from w liich the processor at- 
tempts to execute sturcessive instructions. Operations from 
witliin the cache aie inherently much faster th^m operations 
that require accesses to external memory. The nucroproces- 
sor's caclie control unit attempts to keei> ^h*^ cache filled 
with the most ciurent set of instnictions antj data. Only 
when the processor needs ncw^ mstiuctions or (lata in its 
uitenial cache does tuiy obsen^able bus activity occur If the 
cache is large enouglu and "large enough" is loosely defined 
as when bothi possible destinations of a program branch are 
contiuned m the cache, then Umg periods of tune can go by 
wilhf.Jut k\ny obsen'able bus activity, hi such a situation, a 
software performance analyzer is virtually useless. 

A designer might solve tins dilemma by instnicting the mi- 
croprocessor to turn off the mtemal caches, tliereby causing 
all accesses to go to external memory. Tliis woukl solve the 
problem, hut the system would obviously not be nuining at. 
full speed. An alternative solution is to insert certain instruc- 
tions called markers into the code. The maikers instruct the 
microprocessor to perform writ:e operations to external 
memory or I/O space at critical U>cations in the program, 
such as fimction entry or exit points, or wiieu the embedded 
operating system initiates a task switch. The software per- 
fomtance analyzer can then he configuretl tu record and 
make measurements based upon these marker-based events. 


The software performance analyzer ts capable of making a 
variety of software performance measureiuents. These 
measurements answer the questions: 

* Why does it take so long to execute my program? 

• Which modules are si owning down overall program 

• How intensive is my program *s use of data or I/O ports? 

* How^ much time is spent getting between various points m 
my program? 

^ Which function is called most often? 
Wliich functions are taking the most processor time? 
Wliat is the time distribution of calls to my functions? 

Activity Measurements 

Activity measurements are bus cycle counting measure- 
meiUs designed to present the user with aji overlie w^ of how 
a program is using the microprocessor resources. This tyiiie 
of measurement provides answers to the first three of the 
above quest ions. These riK^asurements can reveal which 
hbraiy a |>r<jgrajn is execiUiitg in uiost of the time, or huw^ 
often a region of program space is being accessed. 

Memory Activity Measurements. The software perfom\ance 
ajiaJyzer makes two lypvs of activity measurements. The 
fij-st is a raw count of cycles. This measurement will show 
how intensive is the use of data or I/O ports. Tlie software 
perfomiance atialyzer counts cycles and recoids the dma- 
tions of cycles by sequentially scannmg each of the memory 
regions being monitored. If a cycle of a particular type oc- 
curs in the memory region being motiit.ored, it is comited. To 
make this measurenient, each of the specified mem 013^ re- 
gions of a user's program are inspected oru^ at a time for a 
period of 2.6 n\s. All cycles of the specified tyi^e in tins mem- 
oiy region are comited. In addition, a tinier records and 
smns the lengtlvs of these counted cycles. At the end t>f the 
2.5-ms period the results are recorded and the next memory 
region is inspected. 

After scammig each of the user's memory regions once, the 
analyzer has, in essence, ccjmpletely dissected a 2.5"ms 
trace of all cycles for all memory regions. It used approxi- 
mately 2.5 ms times the number of memory regions to do it, 
and it looked at different samples for each mejnory region. 
Assuming tliat the user's program is repetitive, tJie statistics 
of this sampling will approximate the true execution of the 
program. A n\axinuuu of 254 user-defined memory regions 
can be inspected once each to capture 2j5 ms of trace in 
approximately 640 ms. 

Fig. 2 shows the result of a tjiDical memory acti\ity measure- 
ment. Tills measurement shows that the user program is 
spending 17% of the execution time of the processor access- 
ing a memory region labeled data. The majority of the pro- 
cessor's time, {J6%, is being spent accessing memory' regions 
lliai are u<.)l tlefmed. Tlie amoimt of time that has been com- 
pletely j>n>cfr=ssed is 5. »3 seconds. This implies that if you 
could make a trace of all cycles for 5.3 seconds and sort all 
of the cyties into the appropriate menioiy ranges, a display 
like that of Fig. 2 woiild appear, 

A limitation of this type of cycle comiting measurement 
occurs in t rying to measure the pej-fonnaiice of a prr^gram. 
Raw cycle counts do not give an adequate measurement of a 
function's perfonnaiice because they exclude memory cycles 
associated with program execution. Consider the example 
of trying to measm'e the peifonuaiice of the two functions. 
a_func and b_func. One measurement of the performance of 
a June aiui b_func using a raw cycle comit of memon/ activity 
might yield a histogram like Fig. 3a The undefined activity 
Ls the activity associated with reads and wiites to the stack 
and variables. Variables in embedded programs are tyijically 
located outside the address range of the instructions of the 

lOS .^pril 19^ HewlMUPat-kard Jnuma] 

)Copr. 1949-1998 Hewlett-Packard Co. 


Run Time: Ch32 



% m 






mdk 2 


Undefined Addresses 

924,3 ms 

800.6 ms 

29.3 ms 

24.S ms 


3.5 s 

17 77 

1 f J/ 



FrofilBd Absolute 








Fig. 2. Software perfomiaxice 
analyzer memory activity mea- 

fuiicdoii, Tiius. iUr cycle eoimtiiig (memoo' aciKlty} n^ea- 
suremenT only records opcode fetches or iitstruclion eK€^u- 
tion in the range of the ftmction and rtiisses the associated 
read and write operations that occur outside the range of 
the fiinc'iioa 

Program Activity Measurements. A different activity niea^iire- 
ment o\er comes this liioitation by using the opcode cycle as 
the key cycle to detennine if cycle recording should be 
turned on or off. If the opcode cycle is m the active nienioiy 
region it v^ill he recorded, but in addition all other cycles 
occuiTing after il will also be recorded tmtil the nesi op- 
code. Tills allows the software performance anal>^zer to re- 
cord the opcode and all cycles associated with the opcode, 
h) this program activity measurement, all of the time will be 
properly di\ided among all of the active functions, us showTi 
in Fig. 3b. The undefined cycles are allocated to the func- 
tions that generated them, thereby giving a more correct 
understanding of program operation. 

Fig. 4 shows the results of making a program activity 
measurement. The histogram in Fig. 4 shows that the 
applv_productiDns module is using most of the processor re- 
sources (51%). The tabic in the lower half oF Fig. 4 is jusl an 
expansion of the infommtion shown in tile upper histograjn. 
A variety of additional infonnation is provided for each of 
the captured ruentory regioi^s. In particular, the number of 
cycles and the loial tinie that the cycles have been active are 
recorded. The lime per cycle is a measure of the average 
execution time of a cycle. The mean is aji estimate of the 
anunn^t of time that each memory region is active in a one- 
sec oml I period, Ttie standard deviation or variance indicates 
the variation about tJie tnean. 

The advantage of program activity iueai>urenients is that 
they allow the user to define events that, cover large seg- 
inenls of memoiy. The user can ^lefine an event for each of 
the libraries of a program, and the software performance 
aiKilyzer can Quickly detennine which library is using the 
most processor resources. Witii this infomtation, the user 

H_tunc 30% 

bjiinc 307o 
Undefined 40% 

ajunc 46% 

hjunc 54% ^« 

Undefined 0% 


Fig. 3, Soft, ware perfortnance aniily^er attivity mea,'5ijrements, (a) 
Mf 'iT)i iry afUviLy nieasnrenxent. (h) Progjani activity measureHient, 

can define events to represent each of the functions in the 
slow library^ and make a new profile measurenteiu to find 
out which function is taking too much time. 

After isolating in a general manner the libraries and modules 
that are taking too long to execute, tlie user can focus more 
directly on exactly which functions are perfoniing poorly. In 
addition, it can be determined if a function (such as malloc) is 
being called too often or if a function is on occasion beha%-- 
ing in an unexpected manner, leading to a single long execu- 
tion rime for the function. Finally, the user can examine ihe 
time betw^een specific poitus of the program and determine 
if time-critical intervals are within specifications. 

Duration Measurements 

A software performance analj'^er dtuation measurement 
answ^ers the last four questions listed above. Duration mea- 
surements are real-time, nousanipletl measu rente nts. The 
measurements continuously capture inlonnation about all of 
the fimctions or intervals selected. No sampling occtus and 
eacli start aitd exit of each of as many as 84 fmictions or 
intervals are continuously recorded. Tlie only limitation is 
that function or interval start and exit address events must 
not continuously occur at an average r"ate higher than one 
eveiy 100 ^s. Bursts of less than 500 events can be handled 
even if they aie only n^moseconds apart , but continuous 
sub-100-^s interv^als will lead to situatiorus where the soft- 
ware performance analyzer cannot, keep up. This will be 
explained in more detail later and in most typical situations 
is not a constraint that a user has to deal with. The software 
performance analyzer am tnake interval and three difTerenl 
function duration measureinetits. 

Interval Duration Measurements. Interval duration measure- 
ments are address point-to-point measurements. These mea- 
siuements reveal how long it takes to get from one point to 
another in a program. To make this metisnrement, the soft- 
ware performance ;:maiyzer isolales [he itnique address 
points, qualifies the address points with tJie proper status, 
and then stores the address points ;Ut>ng with a time tag. A 
dedicated software performance analyzer microprocessor 
then evaluates and matches the start and end points of each 
inteival and generates an event occurrence. The time associ- 
ated with the event occurrence is calculated and tabulated. 

The dedicated software performance analyzer micropro- 
cessor can process a stail and exit pair ai\d do all of the 
associated math tabulation in less than B5 [oicroseconds. 
The results of an inteival dtuation measurenient are then 
transmitted to the host interfacen w[\ich translates the saved 
values into floating-point values and i)t esents the results to 
the usen 

April imS Hewlett-Packard JouniaJ 1 Of* 

)Copr. 1949-1998 Hewlett-Packard Co. 



% m^ 


Run Time: D'^l 




a pp ly_p rfidu i^IiajTS 
scan stri rig 
UnrTefined Addresses 

2.6 s 
8Q2.1 ms 
354.8 ms 
241.5 ms 
218.4 ms 
dB4.2 ms 

■;i <^ 

J 1 .3v 



Piafiled Absolute 

5.2 s 

lOO^i- 0% 








Time: 0:31 




Time % 

Mean! Is) 



apply productions 




515 J ms 

443.4 ms 




802.1 ms 


157J ms 

254,4 ms 

536.8 ns 



354. G ms 


G3.5 ms 

2^7 4 ms 

530.1 ns 

math librarv 




47.3 ms 

119.9 ms 

544.8 ns 



218 4 ms 


42.8 ms 

132.3 ms 

536.8 ns 

Undefined Addresses 


964.2 ms 



Profiled Absolute 


5.2 s 



Fig. 4, Software perfonnance 
analyzer pro^miTi activit^'^ niea- 

suffiTient hjslogram and table. 

A typical interval duration measorement is shown in Fig. 5. 
Different intervals can be measured, such as the time from 
the exit of a_func to the entry of a June or the time between 
successive ctiUs to b_func or the time between the start, of 
c_func and the start of ejunc. The interval duration table pro- 
vides additional information about the interv^al dm-ation 

Function Duration Measurements. Function duration measure- 
ments are jrieai)Urenient.s of the length of tmic it takes a 
function to execute. *fhe software perfonnance analyzer can 
make three types of function duration measurements. These 
are ftmction duration including all calls, furiction cluration 
excluding all calls, and function duraliort excluding profik^rl 
caOs. The first (function duration including all calls) will 
measure the time from the start of die function to the end of 
the fund ion tmd include aU time spent executing code asso- 
ciated with functions that are called from a function. This 
uicluding calls measurement will also include time servicing 
an intemipt if an intemipt occurs in the middle of a fimction 
being measured. 

The second duration measurement (function duration ex- 
cluding all calls) will only record the lime spent executing 
the selected function. All calls and all time spent ser\icing 
interrupts w^ill be excluded from the nieasurement. 

The third duration measurement (function diuntion excluding 
profiled calls) will tnchide into the measurement of fimction 
dmation all time associated with the fimction and aU calls 

except those fmictions that are also being profiled. An inter- 
rupt function will be included or excluded from I he time 
associated with the measurement of a function depending 
upon whether tiie interrupt is being profiled. 

To make fimction duration measurements the software per- 
formance ajiab^zer isolates the start and end address points, 
qualifies the address points with the proper status, and tJien 
stores them ;dong with a tinie tag, Tlie dedicated softwaie 
perfonnance analyzer microprocessor then reads the stored 
events J matches the start and end pou\ts of each f miction, 
and generates an event occurrence. The time associated 
with the event occunence is then calculated and tabulated. 

All this is similar to how interv^al durations are calculated 
except that two additional hardware and dedicated micro- 
processor operatioris are required. Tlie software perfor- 
mance analyzer hardware, in addition to isolating the start 
and end points of a fimction^ ^\ill also recognize the address 
range of a function. This is used with the excludir^g all calls 
fmicrion duration measurement to stop m\ internal timer 
when the function being measured is not in range. 

A second hardwaie consideration is the prefetefi correction 
circuitry. Prefetch correction circultiy renioves 90% of all of 
the prefetches associated with tiie start and end address 
points of a function. A program loop near the exit of a pro- 
granT may prefetch the exit and possibly the entrance to a 
seconti function. An algorithm using the in-range feature of a 
function removes most of tius prefetctiing. Addresses that 




h_fiinc fi_fuiic 

c_fiinc e_func 

Undefined Addresses 

Profiled Absolute 


% 0% 

1D.1 s 

3.9 s 




10.1 s 

100% 0% 














Time % 




Std Oev 

a_fiiiic_end a _f unc 

c fuiic_e June 
Undefined Addresses 



12.5 ms 

3.9 s 






10.5 ps 
85 ms 
37 ms 

10.5 ^i£ 
3.2 ms 

3.2 ms 

0,0 ps 

Profiled Absolute 




Fig. 5. Software performance 
anr*ly^er interv^al duration 

1 ID April 2993 Hewlett Patkiuxi JouhtkI 

)Copr. 1949-1998 Hewlett-Packard Co. 


e ItHK 

!^ I 


I ^ -Colls- 

Fig, 6, Exrmiplp prograni. Function ajum. is called repetitively: 
Function ajunc calls bjunc. and so on. 

are prefetched and get thrrnigh the hardware correction 
algorithm are then topically removed by the dedicated soft- 
ware perft>rmance analyzer microprocessor. The softw^are 
perfonnaxice anal^Tcer microprocessor contains an internal 
jstack that attempts to mimic the call stack of the program. 
This stack contains each of the function stiu1 calls, Wlien a 
function exit occturs the stack Ls searched to find tlie apprtJ- 
priate function entr>\ Algoritiims used in association with 
the call stack attempt to minimize rhe occurretire of unused 

Consider the case of the five functions (ajunc, bjuncn cjunc, 
rijunc, ejunc) all of whk'lt are identica! In execution time. 
Assume that a_func calls b.func^ wMch in turn calls cJunc, 
which then calls djunc, and linaliy, d^func calls ejunc. ALso 
assume that a_func is repetitively called so that as soon as 
a_func exitSt it is called again. 

A picture of the execution of these functions might look 
somefiting like Mg. ix Assume that the user only nieasures 
functions a_func, b_func, and c_func. Software performance 
tmalyzer measiu^ement.s of these functions might show re- 
sitits like those shown in Fig. 7. Obser\'e the differences in 
the three tyj)cs of duratioti measurements. Each measure- 
mvT\\ prf>\ides information about the duration of a function 
in ii n^aiTner that a user may want to obsen^e it. 

Call Stack. The dedicated software perf<:»rmaiice ai^alyzer 
microproces^sor is responsible for conibinin^ start ancj exit 
function events to create a fimction duratioit time. A simple 
approach is just to subtract the time associated witli the 
entr>' even! fron^ the exit event time to create a Lime dtira- 
tion. This will work in an uiclucUng calls measurement but 
not in an exehtding calls measurement. The excluding calls 
measurc^nient nuLst subtract out the time of called furictions 
from the duration of the function currently being measured. 

Tb overcome this limikLlitm and others involving prefetch^ 
the dedicalcd s<ifrvvare perfonnance analyzer microprocessor 
uses its duplicate call stack. Proper calculation of function 
durations is dependent upon the validity of this internal stac^k. 

Statistics. The dedicated software performance an^dyzer 
microprocessor is respfjnsible for determining ftmcti(jn or 
inten^al duration and sunuuini^ lite duration results for sta- 
tistical imalysis as (|iii< kly as possililc ( < U^^} M^J riie ap- 
proach taken is to use integer math and avfjid floating-point 
conversions and floating-poini matli. Thus, every event dm-a- 
tion thai is recorded is summed itUo a total duraiion for the 

particular event. The event duration is then compared to the 
current maximum and minimum values to determine these 
statistics. Finally, the event duration is squared and sunmied 
for a standard deviation calculation to be performed later. 

Each event is summed by the dedicated software perfor- 
mance anidyzer microprtx^essor into an event histor>; which 
resides \%1th the dedicated software performance anal\'zer 
microproc^sor. The integer v^ues are moved to the host, 
converted to double-precision floating-point values, and 
processed by the host, processor to generaie the maxunum, 
minimum, mean, and standard deviation values presented to 
the user 

Aiidress Alignment A user interface feature is the ability of 

the uiterface to look up function and static variable svTuhoIs 
automatically and define events for them. It does this by 
examining the symbol data base and locating function and 
static variable symbols. These symbols are converted to 
address ranges that are aligned to the microprocessor fetch- 
ing address. For example, the microprocessor addiess range 
of a function may be 1002h through I247h. The fetched ad- 
dresses of this microprocessor may be on 4-byt.e boundaries 
and may appear as lOOOh and I244h, The software perfor- 
mance anal.vzer corrects for this and defines ttie start of this 
fimction on the occurrence of address 1000b and the exit of 
tins function on the occiurence of acidress i244h. 

A second problem now appears if a function precedes the 
fimction discussed and ends on address lOOlh. If this pre- 
ceding function is also aligned it will appear to exit on ad- 
dress lOOOh while the second function starts on address 
iOOOh. This then becomes a problem for tht^ software perfor- 
mance analyzer that is impossible to solve. If adtiress lOOOh 
is observed, Ls it a function exit or a fimction entry? To cor- 
rect this problem the software pcrl'omiance analyzer allows 
the start and exit adtlresses to be ac^justed. bt this particular 
situation the user may wish to push the start addresses for- 
ward by two bytes so thai the t\ew st<u1 address of the origi- 
nal function is now on the fetched address 10()4h instead of 
KlOfih. AdjusliTv^ Hit' addresses Ui align fhem on 32'bit 
(4-byt ej liouiKiai ns will sonietinu\s ijUroduce a small errors 
which is insignificant in most cases. 

Markers. If a ustT is using markers, the software performance 
iuialyzer will atttomatically tlefine both the ad (iress range of 
the fimction and the start and end afidresses of the markers. 
The function duratitm and interval duration measurements 
will t hen use the marker addresses. 

Markers are write statements placed at the start and end of 
each fmicrion. Tlie software performance analyzer uses 
these statements to determine function duration and inter- 
val duration. One advantage of markers is that tlie user can 
turn on the microprocessor instRJctitJn taoli*^ and data 
cache (provided that write stalenients can write through the 
cache) and the software performance ;iiialyi!er can stiQ 
make valid peiformanoe measurements. 

To use the marker feature of the softw^are performance atva- 
lyzer, eeriaiti conditions need to be satisfiecf The software 
I^erformance analyzer must have unique start and etici ntark- 
ei^ for eacii function that is to be measurett The best way to 
provide these is to add two static variables (unsigned short 

April 1993 Hewlptt-Paiikard Jtjurriii] 1 1 1 

)Copr. 1949-1998 Hewlett-Packard Co. 

FiincitiDn Duration Include CaJIs: 
Name Tiwt 






1 a funB 

10.2 s 


19.Z ms 

99 7S 

2 b fufic 

79 85 

3 c func 

Undefined Addresses 


Piafiled Ahsoliite 















Sid Dev 

1 a_fiine 

2 b_funE 

3 c fur^c 
Undefined Addresses 





19.2 ms 


10.2 ms 
6.1 ms 

10,2 ms 
61 ms 

10.2 ms 
6.1 ms 

0.5 |is 

0.5 ^s 

0.5 ^is 

Prof tied Absolute 


10.2 s 

Functiijn Duration Exclude Calls: 



% 0% 






1 a func 

2.0 s 
2.0 s 


2 b_f unc 

3 c func 
Undefined Addresses 

19 9S 

ZO 01 


Profiled Absolute 

10.2 s 

100% 0% 













Std Oev 

1 a func 
Undefined Addreisses 

we 1 

106 ' 






2.0 ms 
2.0 ms 
2.0 ms 

2.0 ms 
2.0 ms 
2.0 ms 

2.0 ms 
2.0 ms 
2.0 ms 

0.5 ^s 
0.5 \i& 
0.5 ^s 

Profiled Absolute 


10.2 s 


Function Duration Exclude Prof i led: 



% &Vd 






1 ajanc 

2 b_f unc 

3 c^func 
Undefined Addresses 

2.0 s 
2.0 s 
9.2 ms 


60 01 


Prcfrled Absolute 

10.2 s 

100% 0% 









Time % 




Std Dev 

1 a_func 

2 iijunc 

3 cjunc 
Undefined Addresses 





2.0 s 
2.0 s 
9.2 ms 


2.1 ms 

2.0 ms 

6.1 ms 


2.0 ms 

6.1 ms 

2.0 ms 

2.0 ms 

6.1 ms 

0.5 |L5 

0.5 ^s 
0.5 ^s 

Profiled Absolute 


10.2 s 

100% f 

to save meriioiy space) to each fimctioii that the user wants 
the software performance analj^er to nieasme. 

The names of the stait variable and the end variable should 
be the same as the name of the function with t.lie addition of 
a prefix. For example, the tunction main could have a start 
vailable labeled s_main and an end variable labeled e^main. At 
the start of the fundi an a vtUue nmst be assigned to s_main. 
This can be zero or any other value, since the software per- 
formance analj^er does not read data ^^alues. Similaily, at 
tlie end of the fimction a value must be assigned to the vari- 
able e_main. Tile user must write values to ttie markers be- 
cause the soflware performance analyxer is 1 (joking? fcfr 
wTites to these specified variables. If tlte user chooses to 
use tlie prefix s_ lor the start maiker and e_ for the end 
marker of a function, these same prefixes must lie used ftu' 
all functions that the user wants the software performance 
anal^j^er to recognise. 

Fig. 7. Three t>T^s of soft^v^are 
perfurniiuice anal^^^ier functiun 
duration measure tnents for the 
exam pic prDgnim of Fig, fj. 

One method of adding markers to a program is to add #ifdet 
statements at the appropriate places, as sho^^Tl in Fig. 8. 1Tie 
use of tlie #ifdef statements will allow the user to conditionally 
compile the markers in atui out of the code. 

To conllgure the softw^are performance analyzer to use mark- 
ers, the user sets tlve shell variable HPSPAMAflKERS- 'yes s_ e_" 
before starting the emnlaiion session. All ftmctions then 
defined will pick up the full address ranges of the fmiction 
atid miu-ker addresses. The marker addresses will be auto- 
matically used to make function and mterval duratioti 

Software Performance Analyzer Architecture 

Tlie block diagiam of the HP B1487 software perfonnimce 
iiiialyzer is shown schematically in Fig. 9. The ilP B1487 
hartiware consists of three main sections: the microcontroEer 
core, the data acquisition section, and tlie host interface. 

112 April 1P9;1 1 [ewlptt-Pafkarti .[( mnuil 

)Copr. 1949-1998 Hewlett-Packard Co. 


static: s^ort int sjestvalut; 

ststFC slrort im e_ie5?¥a1u«; 


testvaluef myva I ue I 
im myvalue: 


#ifde1 MARKERS 

£_test¥alue = 1fc 


if (mfirplifolIXII 

#ifdel MARKERS 

e_t«stvalue = 0; 


Mififef MARKERS 

e tcstvaluc^O; 

rfltum( FALSER: 

Fig. 8. t ^sing ifdefe to Insert markers In a ftjnctioTi. 

The nikToconti'oller core consists of a processor, 2o6K bytes 
of RAM, 128K bytes of electrically erasable ROM, interrupt 
control, and a delta- time interrupt generator. The microcon- 
troller is responsible for coordinating and sequencing all 
aspects of the nicasnrement system. This includes prograin- 
ming of the hardware for the specified measurement and 
processing the results into a format that is suitable for trans- 
mitting lo the host- Because^ of the lar^e amoimt of liigh- 
speed data processing required, a fiBhX'O^O was chosen as 
the controlling processor 

The ROM holds all of the operating iuu\ performance verifi- 
cation code (firmware). Since ROM is slower than RAM, the 
contents of the ROM are copied into RAM after reset. Delia- 
time interrupts are general ed every 2.n nis by a down- 
counler derived from the processor clock. These interrupt.s 
are used to iniplement a real-time clock and help to control 
activity measurements that are ninning in a statistically 
sampled ntode. 

Analysis Bus 

Addro«s Status 

Host Bus 

Fig, 9. liardwart' Uloi k \JjuJ>inijii ui" itu' tlP 11187 software ptTformance 

Data is transferred between the HP B1487 and the HP 
64700A emulation cardcage \la the host interface. This inter- 
face consists of a dual-port RAM (8K by 16 bits) and a con- 
trol register UTien the cage is first j>owered up, the micro^ 
controller is held in a reset state. The software performance 
BBsdyzer is released from r€?set when firmware changes the 
state of the reset bit in the controj register. 

Data Cand commands) are exchanged between the host and 
the microcontfTolier \Ta dual^ort RAMs, When the host wTites 
lo a command location \ddwi this memory- a microcontroDer 
interrupt is generated. The microcontroller reads the com- 
mand location^ clearing the intemjpt. It then processes any 
data that the host has placed in the RAM. 

UTien the microcontroller wants to signal the host it writes 
to another command location within the RAM. Tfiis action 
sets a bit in a status register that is %isible to the host pro- 
cessor in the cardcage. ^\Tten the host sees this bit set, it 
reads the comnuuid location and t^lears the bit. 

The data acquisition section performs the actual measure- 
ments. Fig. 10 is a simplified schematic diagram of this hard- 
w^are block. Its main components aie ranging hardware, 
counter/timers, state machines, and high-speed first-in, 
first-out (FIFO) buffers. 

The ranging hardware is responsible for identifying the in- 
conmig events. An event can be a 32-bit address or address 
range. The range comparators are cor^structed using 
C>4K-by-l-bit high-speed static RAMs. Tw o stages of RAMs 
tire used with a pipeline register between lliern. Witliout 
pipelining, the goal oi'25-MHx operation could not have been 
met within cost goals. The range information is programmed 
into the RAMs t>y the onboard microprocessor from data 
provided by die host workstation. Tliese higli-speed RAMs 
are called compare RAMs. 

Mciisuremenl control is handled by two state machines. One 
is used for ihe activity measurements and the otlier for tlie 
time duration measurements. The slate machines are imple- 
mented in [m)grajunml>le array logic (PALa), one PAL for 
each suite machine. PALs gave us the tlexibility to change 
complex measurement algorithms during development. 
They also allow for field upgrading and enhanced measure- 
ments m the future. 

Activity Measurement Hardware 

All measurements mvolve the counting or timing of events^ 
Tills requires the design of two sets of counters, one for 
comiting events (state counting) imd one for counting 
ela].>sed time. Storing or sampling of time ct>unts requires 
careful design. The counter must be able to run at high 
speed to give the time resolution needed. It must also have 
sufficient width to record long ela|)sed limes. This often 
leads to the counter's still changing its output state long 
after the input clock tick has arrived. 

To solve tills problem a tjray-cude count sequence is used. 
Gray code permits only one bit to chruige per clock pulse. If 
Uie store strobe (the signed that reads the <'!ock state) oc- 
<ui"S during a coimt transition I he maxunum error is ±1 
count. Since the clock source is 5(1 MHz, tliis translates to a 
±20-ns error per count store. 

April 1003 Hewrlptt-Parkard Jouni:il 1 1 3 

)Copr. 1949-1998 Hewlett-Packard Co. 



#-- - 

Data tD MicrDDontroMcr 
Addiflss from Micrq controller 


Roll Ov6f 



To Iniorrtipt 




Oata to 

To Internal 
State Analyzer 


'I a? 


Fig, 10, Siiriplilled bloek diagrimi of Ihe data acquisJtiorL section of 
the software (i erf on nance anal^-zen 

One drawback of Gray code counting is thai U\e counts 
must he converted to blnar>' at some point. This could be 
accomplished in firmware, but this w^ould seriously reduce 
the effective tlata processing speed. For this reason tlie Gray 
code is converted to biruuy by a liardwai'e decodii^g circuil» 

implemented using PALs. Conversion time is approximately 
230 ns for a 27'bit Gray-code-to-binary conversion. 

Activity measurement ratvges are defined by programming 
up to 254 ranges into the compare RMls. A second bank of 
RAM, called the decode RAM, is programmed to provide a 
true output when it identifies a current range of interest 
coming from die compare RAM The activity state machine 
obsen^es tJie state of tins sigiuij atuJ the type of cycle in 
which it occurred (i.e., opcode fetch, memoiy tead/v^Tite, 
etc.). The counters are then turned on or off depending on 
the type of activity measurement being perfonned. Each 
range of interest is scimnod for 2.5 ms. At the end of this 
time inlervfij the onboard microcontroller strobes the con- 
tents of all coimters into the sample registers simultaneously. 
The dec:ode HAM is tlien reprogramnied to observe another 
range of interest. By programmijig only the compare RAJVls 
with all of the rimgcs of interest an<J only rcprogramming 
the decode RAM between ranges, dead tune between range 
samples is held to an absolute minimum, Tlie measurement, 
is then allowed to continue for another fixed length of time. 
The microcontroller is responsible for accumulating these 
counts and irausmitting them to the host- 
Duration Measurement Hardware 
The basic fimction of duration rements is to record 
the time betweeji the occurrence of two events in the user's 
prc>gram* Tliese cmi be function entrj-^ or exit points, access 
to memory, I/O, or the processor's writing out markers be- 
cause of instnnoented code. It is very important that the 
duration measurements properly record the time interv^al for 
ever^f^ executiori under observation. Therefore, a large frac- 
tion of the design effort was spent to ensure that data would 
be acquired by nonsampbng itiethods. This ensures that all 
interval execution times, no matter how small, are repre- 
sented in the measurement resiilt-S. Also, inaxinnmi time 
resolution w^is required (40 ns) for very long intervals 
(liours). Furl herm ore, it was important to minimize or 
remove the effect of processor prefetcliing from the 
measurement results. 

The design implemented is able to measure up to 84 func- 
tion intervals directly (nonsampled) with a time resolution 
of ±40 ns for very long periods (months ). Up to 95% of pre- 
fetch conditions can be conected for by a combination of 
hardw-are and finnware processing. Measiuement results 
can include or exclude time spent in functions called by the 
function under observ^alion. 

A dmation measurement starts when a qualified event is 
recognized by the address comparators. The dui-ation state 
machine then decides (tiependtng tjpon the measurement 
type) If the event numbej- rmd time should be stored into the 
pipeline register Tlie pipeline register can be flushed if the 
state machine determines a prefetch has occuncd. Any pre- 
vious vahd entries that may be contained in the pipehne 
register are written into a first m, fnrst out buffer (FIFO). 
Tlie state machine considers a prefetch to have occmred if 
the cunent event under observant ion is exited via the hinc- 
tion return point and then is reentered without going 
through the function entry point (Fig. 11), Also, if a function 
is entered more than once without exiting through the re- 
turn point the state machine will flush all but the last entr>^ 
point from the pipeline register The user can defeat this 

114 April 199;1 tknvk-u-Patkard JoLunal 

)Copr. 1949-1998 Hewlett-Packard Co. 

&«r 1 







ExJVSler? in 
PiU^l^ine Register 


Fig, 11. Siniplified prefetch correction state diagram. 

action by marking functions as recursive. The elimination of 
I irefetchcvs presents the FIFO from overflowing when code 
loops exist a1 the end of a funetion. If this situation were not 
[)roperly liandletJ in haidware, prefetches could cause ttte 
HFOs to fiJl faster than the microcontroller could process 
I hem and errors wtjuld occiu-. 

The FIFO provides an interface to the microcontroller. As 
long as events enter the FIFO at an average rate less than 
one everj' 100 us the controOer can contintre to process datii 
in a nonsampled mode. If the FIFO overflows an intemipl is 
seni to the microcontroller and the user is notified- Inter- 
rupts iire jilso provided for lialf cind 75% full The fimiware 
makes use of ihese to delay noncrilical tasks unlil tlie con- 
troller has <*aught np with the data slreani. This billows the 
HP B14S7 to maintain a very high rate of data throughput 

Duration e^'ents may have very large time inlen^tLs between 
tJu^m. To nieasttre large intervals that exceed the maximum 

limit of the time counter (2.6 seconds) the counter provides 

two signals to the state ntachine: half eoimt and fiiM count. 
These signals generate a FIFO store if none is pending as a 
result of an entr\^ or exit. By using these intermediate time 
counts the firmware can compute large time inier\'als 
between events. 

An additional feature of duration measurements is the abil- 
ity to send a trigger signal to the mtemal state analyzer of 
the HP 64700 cardcage whenever an interval exceeds a user- 
specified limit. This is usefiil for correlating a lime limit with 
the state trace of the target microprocessor. This measure- 
ment is limited to one event and a maximimi of 2.5 seconds. 
Tltis is accontplished by first ha\1ng the decode RAM tag the 
inters al of interest by ha\lng the time event signal go true 
when the inten'al of interest is recogitized. The state ma- 
chine then activates a timer when the entr\' point of the in- 
terval is recognized. A comparator monitors the state of the 
cotmter and triggers a flip-flop if the interv^al exceeds a user- 
specified time limit. The counter is reset to zero by the state 
machine when the end of the interval is recognized. 


The HP B1487 represents a significant advance in the field 
of software performance analysis. As an integrated part of 
the HP 64700 product family and the HP 64700 debug envi- 
ronment it helps pro\1de the embedded systems designer 
with the powerful tools needed to design complex and 
dem^mding embedded applications. 


Tlie authors would like tt> acknowledge the efforls of Grant 
Grovenbtirg, tlic IIP B1487 finnware designer, aitd Mike 
Dp ham, who designed the host workstation communication 
protocols, lit atkhtion, we wish to thfmk GraiU for his excel- 
lent paper on the operatioti of his algorithm for program- 
ming the compare liAMs. We regret that spare limilations 
prevented our including it in the fii^d revision of ihis article. 

AfJiii 1993 lie wk'tt'Packafd Journal 115 

)Copr. 1949-1998 Hewlett-Packard Co. 

April 1993 

6 Mrcmwave Signal Generators 

WiniamW. Hemz 

^^sfc. R&D section manager Gill 

y^^^^t Heinz has c on tr i b u ted to the 

J^^^^^ M deveJopment of various 
^^H^SyV microwave components and 
l^K^^W prodijcts at the Stanford 
^^^^V Park Drvision since joining 

^^^^^^j^^ HP in 1968. He initially de- 
^^^H^H^B signed microwave oscNIa- 
^^^^^^^*^^* tors and other microvs/ave 
components and later was a project manager for the 
HP 8B73A/B/C/D synthesized signal generators He 
has also been sectir^n manager for power ar>d noise 
products and microwave sources. Bill was born in 
Havana, Cuba and attended the Polytechnic Institute 
of Brooklyn, from which he received a BEE degree in 
19BD and an MSEE degree in 196Z, He has coauthor ed 
several articles on ferrite devices and is a senior 
member of the IEEE, a member of the Communications 
Society, and a member of the Group on Microwave 
Tlieory and Techniques, in the pasi Bill was actively 
involved in the Boy Scouts and is now a mentor for a 
college preparatory program He has two sons and 
enjoys photography, hiking, listenir^g [o music, and 
traveling abroad 

Ranald E. Pratt 

2 Born in Buffalo. New York, 
Ron Pratt attended the New 
Jersey Institute of Technol- 
ogy. from which he received 
aBSEEdegreeinieS? He 
joined HP's Microwave 
Division the same year and 
developed power sensors, 
nojse source components, 
mixers, ar^d other microwave hardware used in nu- 
merous HP products, For the last ten years, he has 
managed projects in the areas of power measure- 
ment, notse figure measurement, and signal genera- 
tors at the Stanford Park Division, including the HP 
70340A/41A signal generator projects. He contrib- 
uted to the 7th edition of Reference Data for Radio, 
Electronics. Computers, and Communications 

Engmeers. He's also a member of the IEEE and of 
the Groups on Microwave Theory and Techniques 
and ln,strumentation and Measurement. For nearly 20 
years, he taught a microwave measurement course at 
a local college. Ron and his wife have two daughters 
in college. His leisure mteresis include cabinet making 
and coilecting tinplate toy trains. 

Peter N. Rsher 

A software engineer at 
HP's Stanford Park Division, 
Peter Fisher was born in 
Wiesbaden, Germany, and 
attended the Engineering 
School in Dieburg, from 
which he received his Diplom 
Ingenieur in electrical engi- 
neering in 19B2 He joined 
HP's Stanford Par1< Division in 1984. and has developed 
software for a number of microwave products, includ- 
ing the HP 8370 and HP 7Q34Q Series signal genera- 
tors. Earlier, he contributed to the development of the 
HP aSSOA vector analyzer, the HP 3981 A vector mod- 
ulation analyzer, the HP 8782B vector signal genera- 
tor, and the HP 1 1757B muitipath fading simulator, He 
is working on a project to develop a common software 
platform for HP test and measurement products. Peter 
served in Ore German Navy for fifteen months. He is 
married and Nsts board sailing, hang gliding, and flying 
airplanes as favorite leisure activfties. 

12 Fundamentaf Frequency Synthesis 

Brian R. Short 

t Brian Short has been with 
HP's Stanford Park Division 
since 1984 He was one of 
the design engineers for ttie 
RF phase-locked loops for 
the HP B370 Series and HP 
7034D Series signal genera- 
tors Earlier, he was a pro- 
duction engineer and he's 
now designing video test ecfuipmeni Brian was born 
in Redwood Dty, California and attended Washington 

State University, from which he received a BSEE de- 
gree in 1964. He was awarded an h/fSEE degree by 
Stanford University in 1987. His outside interests 
include basketball, softball, and weight lifting. 

Thomas L Grisefl 

Design engineer Tom Grisell 
came to HP ml 965, rbe 
same year he graduated 
with a BSEE degree from 
San Jose State University. 
While at HP he continued his 
studies at Stanford University 
and received his MSEE de- 
gree m 196S. He has served 
as a design engineer for many HP products, primarily 
in the area of frequency synthesis. He was project 
manager fur the HP 8444A tracking generator and was 
responsible for the design of the LO/Re! synthesizer 
assembly and other parts of the HP 8370 Series and 
HP 70340 Series signal generators. He's currently 
working on video products at the Stanford Park Divi- 
sion. Tom was coauthor of several previous HP Journal 
articles and is coinventor of a patent related to fre- 
quency generation for a split-CDmb frequency synthe- 
sizer He's a member af the IEEE A California native, 
Tom ^vas born m San Francisco. He has two sons, is 
an amateur radio operator, and enjoys spending time 
working on his personal computer. 

Edward G. "Sud" Cristal 

A native of St. Louis, 
Missouri, Bud Cristal at- 
tended Washington Univer- 
sity, from which he received 
an AB degree in mathematics 
and a BSEE degree in 1957 
and an MSEE degree in 1958. 
He continued his studies at 
the University of Wisconsin, 
where he completed work for a PhD degree in 1961 . 
He was a senior research engineer at Stanford Re- 
search Institute and an associate professor at 
McM aster University before joining HP Laboratories 
in 1973. After Iransfernng to the Stanford Park Division 
in 1 975, he worked on the development of several 

116 April 1993 Hewlett-Packard JouniiU 

)Copr. 1949-1998 Hewlett-Packard Co. 

signal genefatcus tieiofe bsing named a pnjject man- 
ager He has been a projeci manager for several 
power sensor and power meter products and cofnan- 
aged deveJopmeri! of ihe frequency synthesis system 
for the HP 8370 amJ HP 70340 Series sigiial genera- 
tors. Bud fs the author or coairthor of moi e than 50 
teciiniC3f artiCfes and Has contnbuted to two books 
His wofic on hairpin filter design and meartderlir^ 
transformers has resulted m two patents, He vs^s 
nanred an EEE Felfow in 19B0 and received the lEE 
Microwave Application Award in 1973. He's also a 
memlKrdf the Electromagnetics Academy aod the 
Sffl:iety of Motion Picture and Television Engineers 
He IS married and has two children 

t7 Microwave Gtiain 

William 0. Baumgartner 

A natEve erf Denver, Colorado. 
Bill Baumgartner studied 
electrical engineering ai the 
University uf Colarado. re- 
ceiving his BSEE degree in 
1979 Joining HP's Stanford 
Pari< Division the same year, 
he worked on fiber-opiic 
sources and power measure- 
ment, tfi« hi- bohC/D synthesized signal generators, 
the HP B684f^/Q waveguide power sensors, and noise 
figure nneters He was R5D projeci manager for the 
microwave chain of the HP 70340 and HP 8370 signal 
generator families, and now works on video products. 
Bill IS a member of tt^e IEEE and is active in his church. 
He and his wife and two sons enjoy exploring the 
outdoors while hiking, camping, and scuba divmg. His 
other hobbies include woodworking and toy making. 

John S. Brenneman 

^^^^ D eve lopnient engi neer J oh n 

^^^^^L Brenneman joined HP in 

fli^^^^k 1 983, the same year he com- 

T_jB^BI gleted work for his BSEE 

f^r^ degree from Pennsylvania 

^ = State University He contin 

led his studies whife at HP 
]% an HP Resident Fellow 
■ ' and received an MS£E 
degree from the Urtiversity oMIIinois at Urbana- 
Champaign in 198B He designed the broadband fil- 
ters, couplers, and switches for the HP 8370 signal 
generator family, and in the past designed the micro- 
wave portion of the HP 8971 B noise figure test set. 
Cun'eotly. he's responsible for manufacturing engi- 
neering for the HP 8780/8Z vector signal generators. 
He coauthored two papers on micros trip antennas 
and ts a member of the IEEE His professional spe- 
CJality jS microwave circuit design and his interests 
include antennas and computer-aided design John 
was born in Columbia, Pennsylvania, is married and 
has one daughter He is active in his church, A practi- 
lioner of judo, he has achieved a first-degree black 
belt ranking. He likes to travel and lived in Vienna, 
Austria for seven years. 

John L Imperato 

^^^^ WitfiUFsStaofoftfPark 

^^^^^ ivi si on since 1 983, RSiD 
^^^^^B engineer John Imperato 
VKfl^H resigned the AiC board aod 
^^r^P the GaAs drvider circuitry m 
m^'yB addition to do^ng systen>' 

^il^^L eve I mi crowave power anal - 
^^^^^^^ ^sis for the HP 8370 and HP 
^^^^^ -^^^ 70340 signal generator fam i - 
hes- He also deve toped the algorr^m for calibntfon 
and power flatness correctfon Earlier, he was a micro- 
circuit production engmeer, pioneering production 
shipments of HFs GaAs MMtCs^ Currently he's work- 
ing on video products Born in Rockaway Beach, New 
York. John received a BSE degree in electrical engi- 
neering from Duke University in 1983 and an MSEE 
degree from Stanford University in 1907. Before join- 
ing HP he conducted research related to the treat- 
ment of cancerous tumors with microwave heating. 
John has published ottier technical papers and is 
named as a co inventor in a patent on feedback con- 
trol systems. He's also a member of the IEEE. An avid 
surfer and mountain bike rider, he is an active mem- 
ber of Save our Shores and the Surfrider Foundation. 
He's interested in solar energy and has installed solar 
panels at his home. 

Douglas A. Larson 

With HP since 1984, 

hardware engineer Douglas 
Larson has contnbuted to 
tfie development of several 
microwave products, includ- 
ing the HP 8370 and HP 
70340 signal generator fami- 
lies, the HP 877QA/S arbi- 
trary wavefomi synthesizers, 
and the HP 8791 frequency agile signal simulator He 
IS currently working on the HP 1 1759 Series of RF 
channel simulators. A graduate of Iowa State Univer- 
sity Douglas completed work for his BSEE degree m 
1984 He is a member of the IEEE and his profes- 
sional speciality is mixed analog and digital circuit 

Ricardo de f^ello Peregfino 

A California native. Ric 
Peregrmo was bom ^n Palo 
Alto and attended the Uni- 
versity of California at Davis. 
from which he received a 
BSEE degree in 1983. He 
joined HP's Stanford Park 
^ W /^ Division the same year and 

continued his studies at 
Stanford University completmg work for an MSEE 
degree in 1991 He designed microwave amplifiers, 
mixers, and a UHF attenuator for a frequency agile 
upconvener and contributed to the development of 
the modulation module for the HP B370 and HP 70340 
families of signal generators. He is currently workmg 
in the area of video electronics His other professional 
experience includes work at the National Aeronautics 
and Space Administration and at a radio station Ric's 
hobbies include music, sports, mathematics and 


Gregory A. Taylor 

Development engineer GrK| 
Taylor joined HP's Automaiic 
f^asurements Division in 
1 974 and later moved to tf^e 
Stanford Park Divis ton He 
has been mvoJi^ed m the 
design of various signal 
gerreratofs and noise hgure 
products, and designed the 
1 G-MHz-to-1-GHz sigr^al band for the H? 8373 1 A/32A 
signal generators and the HP 70341 A frequency ex- 
tension rrmdule. He \% currently working on video 
broadcast products. He is a graduate of the University 
of California at Santa Barbara {BSEE 19741 and of 
Stanford University, from whfch he received an MSEE 
degree in communications in 1978. Greg is man-ied 
and enjoys scuba diving, skiing, and sampling wine 
from his collection. 

30 Concurrent Engineering and 

Christopher J. Bostak 

A manufacturing deveh 

opment engmeer at the 
Stanford Park Division, Chris 
His first project was related 
ro the development of the 
MP 83 70 and HP 70340 
signal generator families, 
including the design of the 
fmal tests m manufacturing and design of the com- 
puter network used on the production line. He is now 
developing manufacturing processes and tests for a 
new video product. A native of Fairfax. Virginia, Chris 
received a BSEE degree from the University of Virginia 
in 1989. His MSEE degree from Stanford University is 
expected in 1993. His professional mierests incfude 
digital communications and signal processing. Hobbies 
include cooking, baking bread, hiking, gardening, and 

Damata S. Kolseth 

Industrial engineer Cam 
Kolseth came to HP's 
Stanford Park Division m 
1989 and has been a pro- 
duction enoineer for several 
manufacturing projects. She 
has worked on printed circuit 
hoard manufactunng and 
microcircuit subassembly, 
led the implementation of Kan ban and JIT systems m 
pnnted circuit, microcircuit. and sensor assembly and 
implemented a PC-based database for semi automated 
printed circuit board equipment. For the HP 8370 and 
HP 70340 signal generator families, she implemented 
online video image praceriures, line layout, the mata- 
nal flow strategy, and the process simulation model. 
She's currently involved fn pfanning and executing a 
self -directed work group environment for the division's 
manufacturing organisation Before joining HP she 
worked al Electronic Data Systems and at McDonnell- 
Douglas Helicopter Company as a member of tive 
manufacturing research and development group. She 
is the author or coauthor of two papers related to 
computer integrated manufacturing and is a member 
of the Institute of Industrial Engineers, Cam was barn 

)Copr. 1949-1998 Hewlett-Packard Co. 

April 1993 Hewlett-Packard Joumal 1 1 7 

in Madisan, Wisconsin and attended the University 

Qf Wisconsin \BS Indusinal Engineering 19BG) and 
Arizona State Un^verstty {MS Indus tfial Engineering 
1989) She currently resides in San Francisco, Her 
outside interests include jogging, moontain bicycling, 
and reading, 

Kevin G. Smith 

Born in Alexandria, Louisiana 
and raised in Haustan, Texas, 
Kevin Smith is a graduate of 
the University o( Houston 
(SSEE 1981 land Stanford 
University jMSEE 1 9B6) Be- 
fore joining HP in 1990, hi5 
worked on radio receiver 
design at ESL/Tf^W ar^d nn 
arctic geophysical and oceanoaraphic instrumentation 
for E)oton Production Research For the HP B37Q and 
HP 7Q340 signal generator fami ties, his responsihilities 
included the hardware, aottware, and image integra- 
tion for the pretest process. He was also responsible 
for instrument power budgets for the HP B370 Series 
and for qualiHcatron, modification^ and lest of switch- 
ing power supplies. He is currently v^prking on wide- 
band comn>unications and video projects. Kevin is a 
registered prafess^onaJ engineer in Texas, a licensed 
arrrateur radio operator, and active in the IEEE. His 
professional interests include analog and RE electron- 
ics, digital signal processing, electromagnetic com- 
patibifity, anddesfgn-fof-manufacturahility/design- 
far'testabiiity methods. He's married and enjoys 
reading, jogging, backpacking, and tinkering with old 
radios. He comments that he is also trying to learn to 
play Scottish bagpipes as welJ as his father does. 

38 Mtorowave Sweepers 

Alan R. Bloom 

A design engineer at HP's 
Microwave Instruments Divi- 
sion, Alan Bloom was horn 
in Gettysburg. Pennsylvania 
and attended Wesleyan 
University iBA physics. 19721 
and Rensselaer Polytechnic 
Institute [MS engineering, 
1976) He designed radio 
equEpment at an Ohio firm before joining HP in 1979, 
He has been a components engineer and designed 
most of the printed circuh hoards for the HP e3550A 
RF plug^n. For the HP 83750 family of sweepers, he 
designed the CPU, timer, sweep generator, and rear- 
panel boards and developed firmware for the DSP He 
has written articles for amateur radio magazines and 
sections of several amateur radfo books An amateur 
radio operator [NIALL Alan also enfoys dassical 
music and remudeimg his home. 

Jason A. Chodora 

A California native, EfSiD 
engineer Jason Chodora 
was born in San Jose and 
attended the University of 
California at Berkeley He 
received a 6S degree in 
electrical engineering and 
:ompoter science in 19B3 
and came to HP the same 

year He was a product inn engineer at the Network 
Measurements Division for the HP 83590 Senes RF 
plug-ins and designed analeg circufts for The HP 
83597 A RF ptug-m He designed the synthesis and 
automatic level control circuitry for the HP 83750 
Series sweepers. Jason is married and has a young 
son. An avid golfer. h& jokes that he works at HP m 
his spare time. He also enjoys racquetball and 
camping with hfs family. 

James R. Zellers 

I l^^'^^^^l ^'^ Zellers is R8lD project 

1 // vB manager for HP 837S0 Senes 

^ j'f | ^[ sweepers at HP's Microwave 

tK'\ '^-■'^'^^^jH Instruments Division. With 

^^■' I ^_ fi ' iiiiii-^^^^ served as project manager 
^- HNM^ -^ fortheHPa35g7AD.0t-to- 
g^Km 40-GHz sweeper plug- in, the 

^^^ ' HP 853 spectrum analyzer 
dispfay, and RF network analyzers. Born in Los An- 
geles, he received his BSEE degree from the Universitv 
of California at Berkeley in 1966 and his MSEE degree 
fmm the University of Michigan in 1968. He is rr^ar- 
hed, has two teenage children (one m college), and 
enjoys swimming, hi-fi music, and computers. 

46 Sweeper Microcircuits 

Eric V. V. Fteymin 

a^^^^^^^^^M D eve 1 pme ni e n g i ne er ErFc 
He has worked on several 
40- and 50 -GHz frequency 
doublers and has been a 
production engineer for vari- 
ous amplifiers and escifla- 
tors. Now at the Microwave 
Instruments Division, he 
contributed to the development of the dual VIG oscil 
Eator for the HP 83750 Series sweepers. Eric was bom 
in Wilmington. Delaware and graduated from Lehigh 
University with a BSEE degree in 1980. His MSEE 
degree was awarded by National Technological Uni- 
versity in 1992 He is married ar>d says that working 
on a degree m history has kept him eft the golf 

Bick R. James 

L ^*^^^Br ^ California native. Rick 

M. ^^ iKL ^^^^^ ^^^ ^^^^ '" ^^^ 
m ^f£ '^^^ Francisco and attended 
I I^^H California State Pol^echmc 

W^ " i^^H College at San Luis Obispo, 
^B 4^ ■!■ ^^^^ which he received a 
M. j^vl BSEE degree m 1980 After 

W^^^ /WfcJ ^(>ni^ng to HP the same year, 
u^KmmmBr^^ l^g developed test systems 
for various microctrcuils and MfvtS modules for net- 
work and signal analyzer products. His contnbutfDns 
to tfie development ot the dualYIG oscil la tor for the 
HP B3750 Series sweepers include the, design, test, 
and production engmeering of the 2-lo-11-GHz band 
and the switched amplifier filter detector microcircuiL 
Earlier, he was employed at TRW, where he worked 
an pulse code moduiation tor telephone systems. His 
profess renal interests mclude computer-aided design, 
microwave design, and test system development 

Rick IS married and has a one-year-old son He enjoys 
playing with his son and workmg on his home in 
addition to golf and racquetbali, 

Roger R. Grabber 

^ With HPsince 1972. R&D 
engmeer Roger Graeber de- 
signed the modulator ampli- 
_^jv . ^H herandthe0.01-to-2-GHz 
, C3B|. 'BH heterodyne band microcir- 
cuits for the HP 83750 Senes 
sweepers. Past HP projects 
incEude the HP ^36A power 
meten the HP B6S2A synthe- 
sized signal generator, and the HP 8355DA RF plug-in. 
Born in Oakland, Cafifornia. be completed work in 
1965 for an AA degree in eleclnonics from the College 
of Marin and received a BSEE degree from the Univer- 
sity of Cafifornia at Davis in 1982. Before coming to 
HP he worked on analytical instrumenEs. magnetome- 
ters, and frequency standards at Varian Associates. 
Roger is married and has a son and a daughter in 
college. A train and car collector, his trains range in 
size from HO gauge to three-foot narrow gauge. He 
owns a 1932 Mash and 11 1956 DeSotos, six oF which 
run. He's atso the 1956 Desoto Technical Advisor for 
the National Desoto Clob 

52 3-GHz Pulse Generator 

Hans-Jiirgen Wagner 

^^^H|^^^^| R8tO seed on manager Hans- 
^^Blf^^^H Jurgen Wagner was born 
^H^ ^^^^^1 Ludwigsburg, Germany and 
^Hpil 4^V^H completed work for his Di- 
ll i^ ^^B plom Ingenieur in electronic 
^K T 'i^^H f^cience at the University of 

^^^ {^H Sujttgart m 1984 After ioiO' 

Uj;^ ^^M ing HPs Bdhfingen Instru- 

^^ ^^^ ments Division in 1985, he 

conLribuLeU to die development of the HP B131A pulse 
generator, He was a project manager for the HP 81 33 A 
pulse generator, and now has R&D fesponsibiltty for 
pulse, daia, and function generators He has published 
in the area of GaAs IC design and is interested in 
microelectronics. Hans Jurgen is married and has three 
children. When time allows, he enjoys bicycling, ski- 
ing, soccer, and working on his house. Readrng about 
physics and philosophy is another interest 

56 Pulse/Data Channel 

Christoph Kalkuttl 

Project engineer Christoph 
Kalkuhl joined HP's Sfiblingen 
Instruments Divisjon m 1990 
and contributed to die design 
ol the pulse/data board for 
the HP B133A pulse genera- 
tor, He IS now inveshgating 
digital design characterize- 
tEOn hardware. Born m 
Sigmarlngen, Baden-Wurttemberg, Germany, he stud- 
ied electrical engineenng at die Un>versiry ol Stifttgan. 
from which he received a Diplom Ingenieur in 199D. 
Chri staph 's favorite pastime is musrc. He sings in a 
Choir, plays severaf instruments, and enjoys dancing. 

lis April i 993 Hcrwtett-Parkard J rmrnal 

)Copr. 1949-1998 Hewlett-Packard Co. 

60 3-GW2 Pulse Generator Design 

f^ter Schinzel was bcm m 
SttittgafT. Genntnv and t^ 
ceived a Diplom Injenieur i" 
communications and !heo- 
rettca! electron tcs from the 
"versity of Stuttgart m 

- ■ After join rng the 
dooiingen instruments 
Di VIS ton that same year, hts 
!irst project was workmg on the hybrid technology 
and slope generation for the HP 81 30A piilse genera- 
tor. He contributed to the development of the timing 
boartj for the HP 61 33 A pufse generator and is now 
developing test fixtures. Peters hobbies include 
bicycling and badmmton. 

Andreas Pfaff 

A graduate of the Uniyersity 

t}f Aachen. Ar)dreas Pfaff 
recetved a Diplom Ingenieur 
in electrical engineering 
m 1989. He joined the 
Bcibiingen Instruments Divi- 
sion the same year and de- 
signed ttie output amplifier 
and pulse formatter for the 
HP 6133A pulse generator. He is now investigating a 
new stimulus-response system for digital device 
characterization. He's an ejcpeft in Ihe design of thick- 
film hybrids as packages for high -frequency, high- 
bandwidth ICs. Andreas was bom in Hanau. Germany 
and IS interested m politics. 

Thoinas Dippon 

With HPsince 1391, Thomas 
Dippon is a project engineer 
■■I at the Btiblingen lnstrumer>ts 
Division He was born in 

Stuttgaft, Germany and com- 
J ^k^ ' I pleted work for his Diplom 

ft^B. I I nformatrk from the University 

P^^Hl o1 Stuttgart m 1990. He con- 

tributed to firmware design 
for the HP 81 33 A putse generator, and ts currently 
working on software for digital device ctiaFactefijraiion 
Before joining HP Tjiomas was a software developer 
in the area of computer communications, 

Thomas Fischer 

A mechanical designer at 
the Bbblingen Instruments 
'^■''v^^^ion, Tliomas Fischer has 
•II with HP since 1984. He 
^VdS born in Stuttgart, Baden- 
Wurttemberg, Germany and 
attended the Engineering 
School in Esslingen, from 
which he recetved a Diplom 
Ingenieur in mechanical engineering in 1904. He has 
contributed to the mechanical design of several pulse 
and data generators, including the HP 8175A digital 
signal generator and the HP BOOOO data generator 
system. He worked on EMC. mechanical design, and 
coofing the frequency divider IC for the HP 8133A 
pulse generator Thomas lists CAD software as a pro- 
fessional interest, and model railways, woodworking, 

and reading as leisure activities He ts marned mv^ 
has two sons 

Allan R. Armstrong 

VTithf^ since 1S68.Allaft 
Armstrting is a prDduci de- 
vefopmeni enginiar at HFs 
Microwave Technology Divi- 
sion He has worked on 
putse amplifiers for the HP 
813aA/31 A pulse generators 
and for tfie HP 71 6C4B pat- 
tern generaior, on frequency 
dividers, and on other GaAs ICs He contributed to 
the product engineering, design and design support, 
and development of test methods for the GaAs out 
put amplifier for the HP 8133A pulse generator He is 
currently involved in circuit research on heteroj unc- 
tion bipolar transistor and MODFET processes Allan 
was born in Whitby. England, and is a graduate of the 
Massachusetts Institute of Technola^y jBSEE 1985) 
He is the auttior or coauthor of four technical papers 
and IS a member of the IEEE. His leisure activities 
mclude bicycle racing and touring, photographv. 
htkmg, gourmet cooking, and wine tasting, 

73 Real-Time Frequency Analyzer 

James W. Waire 

Jim Waite has been with 
HP's Lake Stevens Instrument 
Division for eight years as a 
measurement software engi- 
neer in R&D He received his 
BS degree in engineering 
physics in 1979 from the 
University of Colorado and 
his MSE degree in 1984 
from the University of Washington, focusing on the 
areas of digital signal processing and underwater 
ac oust ECS. A member of the IEEE Acoustics, Speech, 
and Signal Processing Society and the Acoustical 
Society of America, Jim takes pleasure in finding 
new applications for digital signal processing in the 
fields of acoustics and vibration His contributionEi 
have included implementing digital swept sine soft- 
ware for the HP 35B5S multichannel dynamic signal 
anafyzer (DSA) and order tracking and real -time octave 
measurements for the HP 35665A iwo-channel DSA, 
Recently, he has been representing Hewlett-Packard 
on several ANSI standards committees dealing with 
noise issues Outside of work. Jim sails a wooden 
boat and enjoys outdoor and travel photugraphy He 
and his family live m a 70 ■ year-old home in a historic 
district near the HP plant. 

82 RMON LanProbe 11 

Maltliew J. Burdfck 

A native of Brooklyn, New 
York, Matt Burdick gradu^ 
atedm 1987 from Indiana 
University at Bloomington 
with BS degrees jn both 

•mputer science and astro- 
.:iivsics. He joined HP's Infor- 

■ jtion Networks Division in 
I iitJB and worked on the 

SNA LU6 2 ^iplTeation pc Dgrammrng Inl^face for i!t€ 
HP-UX Qpef ating system Now at the Network Test 
Dtvtsion, he has worked on earlier versions of HP 
LanProfcs fimware and on the HP ProbeView user 
in^rface More fecently. he was a software devel- 
oper fm Urn RMON Manapmefit information Base 
for the HP LanPrG43e tl. responsible for the filter, 
packet captura, and event groups, Hes currently 
deveSoping ne'W feat\ires for a management staiion 
using the RMON data. Marts professional interests 
include network nianagemeni and SNMP protocol 
He's man^ied and likes reading and scuba diving 

90 EmbeddJed Debug Envrronment 

fiobert D. Gronlufid 

Hnm m Fargo, North Oakcrta, 
~&jh Gionlund attended 
NSorth Dakota Slate Univer* 
sity. completing work tor a 
BS degree m architecture in 
1 990 and an MS degree in 
amputer scier^ce in 1983, 
Before joining HP's Logic 
Systems Division in 1983. he 
designed huiJdmg HVAC systems. At the Colorado 
Springs Division, he has been a member of the tech- 
nrcal staff and an R^D project manager far cross- 
language tools and was project manager tor the HP 
647G0 embedded debug environment He's a member 
of the ACM and the IEEE and specializes in graphical 
interfaces, language systems, and building automa- 
tfon systems. He enjoys tutoring gifted students in 
local public schools, Bob is marned and likes skiing. 
racquetbalL personal computing, and reading 

Rictiard A. Nygaard, Jr, 

Rick Nygaard has been 
with HP since 1977 and is 
an engineer/sciemisi at the 
Colorado Springs Division. 
He has designed hardware 
for several HP logic analyz- 
ers, including the HP 161 tA, 
i^^HH^j*^ the HP IBIOB, and the HP 
'^^^^" ' 64620. He also was proiect 
manager far the emulation portion of rhe UNIX user 
interface for the HP 64D0O-UX microprocessor devel- 
opment system. He was responsible for the emulator 
user interface for the HP 54700 debug environment. 
His work on time-tag counters and RAM- based multi- 
ple range comparison has resulted in three patents 
Rick and his wife are the parents of a son and new 
twins, a boy and a girl. 

John T. Rasper 

A design engineer at HP's 

Colorado Springs Division. 
John f^asper joined the 
«^ |H company in 1979. He has 
^^ i^B ContrFhuted to product devel- 
opment in the areas of de- 
bugger emulator connection 
and vector graphics displays 
and was responsible lor high- 
level debugger system integration for the HP 64700 
debug environment In addrtion to his HP work, he 
has been a software consultant on control systems 
and has developed prmted circuit board prototyping 

)Copr. 1949-1998 Hewlett-Packard Co. 

April im^i UewMi-Pm-kmii JtrnmaJ 1 1 !l 

systems and PBX systems. He is named as an fnven- 
tor in a patent on a camputer-cDntrDllBd system for 
producing printed circuits, H\z professionai interests 
include binJogjca! informatjon processing systems 
and graphics. Born in Tokyo, John attended North- 
western University and received a BSEF degree in 
1976. He's married and enjoys cycling, scuba diving, 
and skiing. 

107 Software Performance Ana [yzer 

Arrdraw J, Blasciak 

An engmeer at the Colofado 
Springs Division, Andy 
B^asciak has be^n with HP 
sinCE?1979, He has worked 
on the HP 643 lOA software 
performance analyzer, devel- 
oped emulator control cards 
and software- based dequeu- 
ers for Intel 3 86 marker tech- 
noSogy, and worked on embedded system software 
performance analysis. He was r^sponsibfe for the . 
overall definiiian and the hardware design of the HP 
B14B7 software performance analyierand is named 
as an inventor in a patent on performance analysis. 
Andy was born at Travis Air Force Base, California 
and received a BSEE degree from Clemson University 
in 1979 Hfs outside interests include skiing, back- 
packing, alpine climbing., and bicycling. 

'■ wt^^ ^^ 

David L Neuder 

With HP since 1979, RSiD 
design engineer Dave 
Neuder was one of the soft- 
ware developers for the HP 
B1487 software performance 
analyzer. Earlier, he was the 
principal software designer 
forthe HP Branch Validator 
and contributed to the deveJ- 
opment of HP Teamwork and the HP 64610 timing 
analyzer Dave was horn in Wyandotte, Michigan and 
is a graduate of Michigan State University (BSEE 
1977 and MSEE 1979) He is named as an inventor in 
a patent on mafking technology in timing analyzers, 
and is a member of the IEEE. Dave is married and has 
a bahy daughter. He enpys singing m choirs, skiing, 
backpacking, bicycling, and mountain climbing. 





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Arf^otd S. Berger 

With HP's Colorado Springs 

and Logic Systems Divisions 
since 1379. RS(D project 
manager Arnie Berger was a 
cathode ray tube engmeer 
for the HP t727A storage 
ascilloscope and v/as team 
|-w:^ leader for the HP 54300A 
probe multiplexer He also 
mar>aged the development of the HP 64700 Series 
emulators and was project manager for the HP B 1487 
software perfonnance analyzer Born in Brooklyn, 
l\Jew York, Arnm attended Cornell University receiv- 
ing his BS degree in materials science in 1966 and 
his PhD degree in the same field in 1971 . His other 
professjonal eJtperience includes work on metal fa- 
tigue at Ford Motor Company and study of crystalline 
defects in oietais at Argonne National Laboratory. He 
is the aothor or coauthor of 25 papers in the fields of 
material science, solid state physics, and technologies 
related to HP products. His work on microprocessor 
development systems has resulted in a patent, and 
he's a member of the American Ptiysical Socfety. An 
HP liaison to schools in his area. Arnie also built 30 
HP 64700A emulators from excessed parts for dona- 
tion to local universities, He is married, has a daughter, 
and likes bicycling and runnir^g. He also enjoys writing 
humorous captions lor the "Immortal Works'' section 
of Electronic Engineering Times, and has had 122 
captmns published 



Hewlett-Packard Camps ny, P,0 Box 51827 
Pslo AltD. GalifQrnsa.. 943C3-{]734 U.S A. 

Vokflgawa-Hewl en- Packard Ltd . Sugmorni'Ky Myo 163 Japan 



)Copr. 1949-1998 Hewlett-Packard Co.